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(R)
ISL3873B
Data Sheet June 2002 FN8019.2
P RE L I M I N A RY
Wireless LAN Integrated Medium Access Controller with Baseband Processor
The Intersil ISL3873B Wireless LAN Integrated Medium Access Controller with Integrated Baseband Processor is part of the PRISM(R) 2.4GHz radio chip set. The ISL3873B directly interfaces with the Intersil's IF QMODEM (HFA3783). Adding Intersil's RF/IF Converter (ISL3685) and Intersil's Power Amp (HFA3983) offers the designer a complete end-to-end WLAN Chip Set solution. Protocol and PHY support are implemented in firmware, thus supporting customization of the WLAN solution. Firmware implements the full IEEE 802.11 Wireless LAN MAC protocol. It supports BSS and IBSS operation under DCF, and operation under the optional Point Coordination Function (PCF). Low level protocol functions such as RTS/CTS generation and acknowledgment, fragmentation and de-fragmentation, and automatic beacon monitoring are handled without host intervention. Active scanning is performed autonomously once initiated by host command. Host interface command and status handshakes allow concurrent operations from multi-threaded I/O drivers. Additional firmware functions specific to access point applications are also available. The ISL3873B has on-board A/Ds and D/A for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates. Both Receive and Transmit AGC functions with 7-bit AGC control, obtain maximum performance in the analog portions of the transceiver. Built-in flexibility allows the ISL3873B to be configured through a general purpose control bus, for a range of applications. The ISL3873B is housed in a thin plastic BGA package suitable for PCMCIA board applications. The ISL3873B is designed to provide maximum performance with minimum power consumption. External pin layout is organized to provide optimal PC board layout to all user interfaces including PCMCIA and USB.
Features
* Supports USB V1.1, and PCMCIA Host Interface * New Start Up Modes Allow the PCMCIA Card Information Structure to be Initialized From a Serial EEPROM; this Allows Firmware to be Downloaded from the Host, Eliminating the Parallel Flash Memory Device * Firmware Can be Loaded from Serial Flash Memory * Zero Glue Connection to 16-Bit Wide SRAM Devices * Low Frequency Crystal Oscillator to Maintain Time and Allow Baseband Clock Source to Power off During Sleep Mode * Improved Performance of Internal WEP Engine * Improvements to Debug Mode Support Tracing Execution From on Chip Memory * Programmable MBUS Cycle Extension Allows Accessing of Slow Memory Devices Without Slowing the Clock * Complete DSSS Baseband Processor * RAKE Receiver with Decision Feedback Equalizer * Processing Gain. . . . . . . . . . . . . . . . . . . . .FCC Compliant * Programmable Data Rate . . . . . . . 1, 2, 5.5, and 11Mbps * Ultra Small Package. . . . . . . . . . . . . . . . . . . . . 14 x 14mm * Single Supply Operation . . . . . . . . . . . . . . . . 2.7V to 3.6V * Modulation Methods. . . . . . . . DBPSK, DQPSK, and CCK * Supports Full or Half Duplex Operations * On-Chip A/ D and D/A Converters for I/Q Data (6-Bit, 22MSPS), AGC, and Adaptive Power Control (7-Bit) * Targeted for Multipath Delay Spreads 125ns at 11Mbps, 250ns at 5.5Mbps * Supports Short Preamble and Antenna Diversity
Applications
* PC Card Wireless LAN Adapters * USB and PCMCIA Wireless LAN Adapters * PCN / Wireless PBX / Wireless Local Loop * High Data Rate Wireless LAN Systems Targeting IEEE 802.11b Standard * Wireless LAN Access Points and Bridge Products * Spread Spectrum WLAN RF Modems * TDMA or CSMA Packet Protocol Radios * PCI Wireless LAN Cards (Using Ext. Bridge Chip) * ISA, ISA PNP WLAN Cards
Ordering Information
PART NUMBER ISL3873BIK ISL3873BIK-TK TEMP. RANGE ( oC) -40 to 85 -40 to 85 PACKAGE 192 BGA PART NUMBER V192.14x14
Tape and Reel 1000 Units /Reel
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved Microsoft(R) and Windows(R) are registered trademarks of Microsoft Corporation. PRISM(R) is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc.
ISL3873B Simplified Block Diagram
HOST COMPUTER
DATA ADDRESS CONTROL
USB
ISL3873B PC CARD HOST INTERFACE USB HOST INTERFACE 1 1 7 IF DAC 6 I ADC DEMOD WEP ENGINE 6 Q ADC PHY INTERFACE (MDI) SERIAL CONTROL (MMI) DATA I/O RXQ THRESH. DETECT ANT_SEL RX_RF_AGC RX_IF_DET RX_IF_AGC RXI
PRISM RADIO RF SECTION
MICROPROGRAMMED MAC ENGINE
AGC CTL
ON-CHIP ROM MEMORY CONTROLLER ON-CHIP RAM
I/O
VREF
TXI 6 MOD 6 I DAC TXQ Q DAC TX DAC TX ADC TX_IF_AGC TX_AGC_IN
TX ALC
7
6
RADIO AND SYNTH SERIAL CONTROL MEDIUM ACCESS CONTROLLER BASEBAND PROCESSOR
ADDRESS DATA SELECT EXTERNAL SRAM AND FLASH MEMORY
44MHz CLOCK SOURCE *
NOTE: THE ISL3873B MUST BE SUPPLIED WITH A SEPARATE CLOCK WHEN USB IS USED.
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ISL3873B ISL3873B Signal Descriptions
Host Interface Pins PIN NAME HA0-9 HCE1HCE2HD0-15 HINPACKHIORDHIOWRHRDY/HIREQPIN I/O TYPE 5V tol, CMOS, Input, 50K Pull Down 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up 5V tol, BiDir, 2mA, 50K Pull Down CMOS Output, 2mA 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up CMOS Output, 4mA DESCRIPTION Host PC Card Address Input, Bits 0 to 9 Host PC Card Select, Low Byte Host PC Card Select, High Byte Host PC Card Data Bus, Bit 0 to 15 Host PC Card I/O Decode Confirmation Host PC Card I/O Space Read Strobe Host PC Card I/O Space Write Strobe Host PC Card interrupt Request (I/O Mode), also used as PC Card Ready (Memory Mode) output which is asserted to indicate card initialization is complete Host PC Card Memory Attribute Space Output Enable Host PC Card Attribute Space Select Hardware Reset. Self-asserted by internal pull-up at power-on. Clock signal CLKIN or XTALIN must be available before negation of Reset. Value of MD[15..0] copied to MDIR[15..0] and various control register bits on the first MCLK following release of Reset Host PC Card Status Change Host Wait, asserted to indicate data transfer not complete and to force force host bus wait states Host PC Card Memory Attribute Space Write Enable USB INTERFACE PINS PIN NAME USB+ USBUSB_DETECT PIN I/O TYPE CMOS BiDir, 2mA, (Also USB Transceiver) CMOS BiDir, 2mA, (Also USB Transceiver) Input, 5V tolerant, pull-down DESCRIPTION USB, MBUS Address Bit 20, or I/O as PL5 USB, MBUS Address Bit 21, or I/O as PL6 Sense USB VBUS to indicate cable attachment Memory Interface Pins PIN NAME MUBE- / MA0 / MWEHMA1-18 PL4-MA19 MLBEMOEMWE- / MWELRAMCSNVCSMD0-7 MD8-15 PIN I/O TYPE CMOS TS Output, 2mA CMOS TS Output, 2mA CMOS BiDir, 2mA CMOS TS Output, 2mA, 50K Pull Up CMOS TS Output, 2mA CMOS TS Output, 2mA CMOS TS Output, 2mA CMOS TS Output, 2mA 5V tol, CMOS, BiDir, 2mA, 100K Pull Up 5V tol, CMOS, BiDir, 2mA 50K Pull-Downs on MD15, MD14, MD13, MD11, MD10, MD09 50K Pull-Ups MD12, MD08 DESCRIPTION MBUS Upper Byte Enable for x16 Memory; MBUS Address Bit 0 (byte) for x8 Memory; High Byte Write Enable for 2 x8 Memories MBUS Address Bits 1 to 18 MBUS Address Bit 19 MBUS Lower Byte Enable, or I/O as PM2 Memory Output Enable Low (or only) Byte Memory Write Enable RAM Select NV Memory Select MBUS Low Data Byte, Bits 0 to 7 MBUS High Data Byte, Bits 8 to 15 Default power up states are defined by pull-up and pull-down internal resistors as shown. Device defaults to external EEPROM for boot up mode. Using external 10K resistors, configure these pins according to Table 4 to change power-up configuration
HOEHREGRESET
5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, ST Input, 50K Pull Up
HSTSCHGHWAITHWE-
CMOS Output, 4mA CMOS Output, 4mA 5V tol, CMOS Input, 50K Pull Up
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ISL3873B
MAC Radio Interface and General Purpose Port Pins PIN NAME PJ4 PJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK7 PL3 PL7 CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA, ST, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA, Pull Down PIN I/O TYPE PE1 LE_IF LED1 RADIO_PE LE_RF SYNTHCLK SYNTHDATA PA_PE PE2 CAL_EN TR_SW_BAR TR_SW SERIAL EEPROM PORT PINS PIN NAME PJ0 PJ1 PJ2 TCLKIN (CS_) PIN I/O TYPE CMOS BiDir CMOS BiDir, 50K Pull Down CMOS BiDir, 50K Pull Down CMOS BiDir SCLK, Serial Clock SD, Serial Data Out MISO, Serial Data IN CS_, Chip Select Clocks Port Pins PIN NAME CLKIN XTALIN XTALOUT CLKOUT BBP_CLK PIN I/O TYPE CMOS Input, 50K Pull Down Analog Input CMOS Output, 2mA CMOS, TS Output, 2mA Input DESCRIPTION External Clock Input to MCLK prescaler (at >= 2X Desired MCLK Frequency, Typically 44-48MHz) 32.768kHz Crystal Input 32.768kHz Crystal Output Internal Clock Output (Selectable as MCLK, TCLK, or TOUT0) Baseband Processor Clock. The nominal frequency for this clock is 44MHz. This is used internally to generate divide by 2 and 4 for the transceiver clock Baseband Processor Receiver Port Pins PIN NAME RX_IF_AGC RX_RF_AGC RX_IF_DET RXI, RXQ, PIN I/O TYPE O O I I I Analog drive to the IF AGC control Drive to the RF AGC stage attenuator. CMOS digital Analog input to the receive power A/D converter for AGC control Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14Baseband Processor Transmitter Port Pins PIN NAME TX_AGC_IN TX_IF_AGC TXI TXQ PIN I/O TYPE I O O O DESCRIPTION Input to the transmit power A/D converter for transmit AGC control Analog drive to the transmit IF power control TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential 29+/30DESCRIPTION DESCRIPTION DESCRIPTION OF FUNCTION (IF OTHER THAN I/O PORT)
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ISL3873B
Misc. Control Port Pins PIN NAME ANTSEL PIN I/O TYPE O DESCRIPTION The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for differential drive of antenna switches The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for differential drive of antenna switches Factory level test pin. This pin must be pulled low with a 10K resistor. Compensation Capacitor Compensation Capacitor Compensation Resistor Compensation Resistor Debug factory test signals. Do not connect Power Port Pins PIN NAME V DDA V DD SUPPLY5V V SSA Vsub GND VREF IREF PIN I/O TYPE Power Power Power Ground Ground Ground Input Input DESCRIPTION DC Power Supply 2.7 - 3.6V (Not Hard-wired Together on Chip) DC Power Supply 2.7 - 3.6V 5V Tolerant DC Power Supply Analog Ground Analog Ground Digital Ground Voltage Reference for A/D's and D/A's Current Reference for internal ADC and DAC devices. Requires 12K resistor to ground.
ANTSEL
O
TestMode CompCap1 CompCap2 CompRes1 CompRes2 DBG(0-4)
I/O I I I I I/O
ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with "-" are active low. ISL3873B Pin Number Assignments PIN NUMBER A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 SIGNAL NAME NC MA10 MA13 MA16 GND PL4_MA19 DBG2 VDD HD3 HCE2 GND HD15 HA9 VDD HA6 NC D1 D2 D3 D4 D5 D6 B1 VDD D7 MA3 MA8 MA7 MA14 MA17 DBG0 GND H1 H2 H3 VDD MLBE MD11 PIN NUMBER C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 SIGNAL NAME HD4 HD6 HD14 HD11 HD7 HA7 GND DBG3 NC RESET G1 G2 G3 G4 G13 G14 G15 G16 MD12 MD14 VDD MA2 GND HSTSCHG HD0 BBP_CLK M1 M2 M3 M4 M13 M14 M15 MD5 VDD GND MD6 VDDA COMPCAP1 GND PIN NUMBER F4 F13 F14 F15 F16 SIGNAL NAME MA5 HD9 HD10 HA2 HA1 L1 L2 L3 L4 L13 L14 L15 L16 MD8 MD7 MD10 MD9 GND RX_RF_AGC ANT_SEL ANT_SEL PIN NUMBER K16 SIGNAL NAME VDD
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ISL3873B
ISL3873B Pin Number Assignments (Continued) PIN NUMBER B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 SIGNAL NAME NC MA9 MA12 VDD MA18 DBG1 HD12 HCE1 VDD HIORD HA8 HWE HA4 NC DBG4 E1 E2 E3 E4 E13 E14 C1 C2 C3 C4 C5 C6 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 MA6 NC MA11 MA15 CLKOUT HD13 MD1 PJ2 (MISO) TCLKIN PJ5 (LE_IF) GND PL7 (TR_SW) PK7 (CAL_EN) VDDA GND VSUB VREF VDDA COMPRES2 NC NC NC F1 F2 F3 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 MD15 MA1 MWEH_MA0 PJ1 (SDATA) NC NC PJ4 (PE1) PK0 (LE_RF) PK3 (PA_PE) RXI+ VDDA RXQ+ RX_IF_DET VDDA TXI+ COMCAP2 TXQ+ NC NC E15 E16 GND MA4 GND NC HA3 VDD HINPACK GND K1 K2 K3 K4 K13 K14 K15 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 CLKIN MOE MWEL GND TESTMODE GND GND PJ0 (SCLK) VDD PJ6 (LED1) PK1 (SYNTHCLK) PK4 (PE2) PL3 (TR_SW_BAR) RXIVDDA RXQTX_AGC_IN VSSA TXIVSSA TXQCOMPRES1 NC PIN NUMBER D8 D9 D10 D11 D12 D13 D14 D15 D16 SIGNAL NAME HD5 HIREQ HIOWR HOE NC HA5 HWAIT SUPPLY5V HREG J1 J2 J3 J4 J13 J14 J15 J16 XTALIN XTALOUT RAMCS NVCS USB_DET VDD USBUSB+ PIN NUMBER H4 H13 H14 H15 H16 SIGNAL NAME MD13 HD2 HD1 HA0 HD8 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 MD4 MD0 MD3 MD2 NC PJ7 (RADIO_PE) PK2 (SYNTHDATA) VDDA VSSA VSUB VDD IREF VSSA NC RX_IF_AGC TX_IF_AGC PIN NUMBER M16 SIGNAL NAME VDD
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ISL3873B
Absolute Maximum Ratings
Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) BGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 100oC For recommended solder conditions, see Tech BriefTB334.
Operating Conditions
Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Electrical Specifications
PARAMETER Power Supply Current Input Leakage Current Output Leakage Current Logical One Input Voltage Logical Zero Input Voltage Logical One Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance SYMBOL ICCOP II IO VIH VIL VOH VOL CIN COUT TEST CONDITIONS VCC = 3.6V, CLK Frequency 44MHz VCC = Max, Input = 0V or VCC VCC = Max, Input = 0V or VCC VCC = Max, Min VCC = Min, Max IOH = -1mA, VCC = Min IOL = 2mA, VCC = Min CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC MIN -10 -10 0.7VCC 0.9VCC TYP 1 1 0.1 5 5 MAX 175 10 10 0.3V 0.1VCC 10 10 UNITS mA uA uA V V V V pF pF
NOTE: All values in this table have not been measured and are only estimates of the performance at this time.
AC Electrical Specifications
PARAMETER CLOCK SIGNAL TIMING OSC Clock Period (Typ. 44MHz) High Period Low Period EXTERNAL MEMORY READ INTERFACE MOE-Setup Time from RAMCS_ MOE_Setup Time from MA (17..0) MA (17..1) Hold Time from MOE_ Rising Edge RAMCS_ Hold from MOE_ Rising Edge MD (15..0) Enable from MOE_ Falling MO (15..0) Disable from MOE_ Rising Edge EXTERNAL MEMORY WRITE INTERFACE MA (17..0) Setup to MWE_ Falling Edge RAMCS_ Setup to MWE MA (17..0) Hold from MWE_ Rising Edge RAMCS _ Hold from MWE_ Rising Edge MD (15..0) Setup to MWE_ Rising Edge MD (15..0) Hold from MWE_ Rising Edge SYNTHESIZER SYNTHCLK(PK1) Period tCYC 83 4,000 ns tS3 tS4 tH3 tH4 tS5 tH5 0 0 15 15 40 15 0 0 ns ns ns ns ns ns tS1 tS2 tH1 tH2 tE1 tD1 0 0 20 20 5 -
SYMBOL tCYC tH1 tL1
MIN 20 10 10
TYP 20.8 10.4 10.4
MAX 200 100
UNITS ns ns ns ns ns ns ns
-
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ISL3873B
AC Electrical Specifications
SYNTHCLK(PK1) Width Hi SYNTHCLK(PK1) Width Lo SERIAL PORT SYNTHCLK(PK1) Clock Period Low Width Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SYNTHDATA(PK2) Outputs Setup Time of SYTHNDATA(PK2) Read to SYTHNCLK(PK1) Falling Edge Hold Time of SYTHNDATA(PK2) Read from SYTHNCLK(PK1) Falling Edge Hold Time of SYTHNDATA(PK2) Write from SYTHNCLK(PK1) Falling Edge SYSTEM INTERFACE - PC CARD IO READ 16 Data Delay After HIORDData Hold Following HIORDHIORD- Width Time Address Setup Before HIORDAddress Hold Following HIORDHCE(1,2)- Setup Before HIORDHCE(1,2)- Hold After HIORDHREG- Setup Before HIORDHREG- Hold Following HIORDHINPACK- Delay Falling from HIORDHINPACK- Delay Rising from HIORDN HWAITData Delay from HWAIT- Rising HWAIT- Width Time SYSTEM INTERFACE - PC CARD IO WRITE 16 Data Setup Before HIOWRData Hold Following HIOWRHIOWRN- Width Time Address Setup Before HIOWRAddress Hold Following HIOWRHCE(1,2)- Setup Before HIOWRHCE(1,2)- Hold Following HIOWRHREG- Setup Before HIOWRHREG- Hold Following HIOWRHWAIT- Delay Falling from HIOWRHWAIT- Width Time HIOWRN High from HWAIT- High BASEBAND SIGNALS Full Scale Input Voltage (VP-P) Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) 0.25 5 0.50 20 5 1.0 22 V MHz pF k MHz tSUIOWR tHIOWR tWIOWR tSUA tHA tSUCE tHCE tSUREG tHREG tDFWT tWWT tDRIOWR 30 20 165 70 20 5 20 5 0 0 92 35 12,000 ns ns ns ns ns ns ns ns ns ns ns ns tDIORD tHIORD tWIORD tSUA tHA tSUCE tHCE tSUREG tHREG tDFINPACK dDRINPACK tDFWT tDRWT tWWT 0 165 70 20 5 20 5 0 0 30 100 45 45 35 0 12,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCYC tH1 , tL1 tCD tDRS tDRH tDWH 83ns tCYC/2 -10 15 0 0 10 4000 tCYC/2 + 10 ns ns ns ns (Continued) SYMBOL tH1 tL1 MIN tCYC /2 - 10 tCYC /2 - 10 TYP MAX tCYC /2 + 10 tCYC /2 + 10 UNITS ns ns
PARAMETER
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ISL3873B Waveforms
ADDRESS MA(17..1)
tH1 RAMCS_
tS1 MOE_ tS2 tE1 MD(15..0)
tH2
tD1
FIGURE 1. EXTERNAL MEMORY READ TIMING
ADDRESS MA(17..1)
tH3 RAMCS_
tS4
tH4
MWE_ tH5 tS3 MD(15..0)
tS5
FIGURE 2. EXTERNAL MEMORY WRITE TIMING
SYNTHCLK tH1 SYNLE SPCSPWR tD1 SYNTHDATA D[n] tL1 tCYC t D2 D[n -1] D[n -2] D[2] D[1] D[0] tD3
FIGURE 3. SYNTHESIZER
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ISL3873B Waveforms
(Continued)
HA[15:0] tSUREG HREGISUCE HCE(1, 2) tWIORD tHA tDIORD HIORDtSUA HINPACKtDFINPACK tDRINPACK tHCE tHREG
HWAITtDFWT HD[15:0] tWWT tDRWT tHIORD
FIGURE 4. PC CARD IO READ 16
HA[15:0] tSUREG HREGNtHCE tHREG
tSUCE HCE (1, 2) tSUA tWIOWR
tHA HIOWRtDRINPACK tDRIOWR HWAITtDFWT tSUIOWR tWWT tHIOWR
HD[15:0]
FIGURE 5. PC CARD IO WRITE 16
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ISL3873B
I
ISL3873B MAC System Overview
ISL3873B MD0..15 MA1..17 NVCS_ MOE_ MD0..7 MA0..16 CS_ OE_ FLASH 128Kx8
SRAM 128Kx8 MD0..7 MA1..17 OE_ MWEL_ MA0/MWEH_ RAMCS_ WE_ CS_ SRAM 128Kx8 MD8..15 MA1..17 OE_ WE_ CS_
FIGURE 6. 8-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873B
ISL3873B MA1..17 MD0..15 NVCS-
FLASH 128Kx16 ADDR(0..16) DATA(0..15) CEOE-
MA0/MWEH-
WE
SRAM 128Kx16 ADDR(0..16) DATA(0..15) UBMLBERAMCSMOEMWELLBCEOE WE
FIGURE 7. 16-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873B
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ISL3873B
LARGE SERIAL EEPROM
MISO (PJ2)
SMALL SERIAL EEPROM
PULLUP
SD (PJ1)
AO SI SCK RESET# SO PULLUP
ISL3873B
SCLK (PJ0)
ISL3873B
CS# (TCLKIN) SCLK (PJ0)
SDA SCL
A1 A2 WP
CS# (TCLKIN) PULLUP
CS
WP#
24C08 (NOTE) NOTE: Must operate at 400kHz AT 3.3VDC
45DB011
FIGURE 8. SERIAL EEPROM INTERFACE
External Memory Interface
The ISL3873B provides separate external chip selects for code space and data storage space. Code space is accessible as data space through an overlay mechanism, except for an internal ROM. Refer to Figures 6, 7 and 8 for ISL3873B memory configuration detail examples. The maximum possible memory space size is 4MB. If USB is the host interface, this is reduced to 1MB. Most of the data store space is reserved for storage of received and transmitted data, with some areas reserved for use by firmware. However, a portion of the data store may be allocated as code store. This permits higher speed instruction execution, by using fast RAMs, than is possible from Flash memories. The maximum size of this overlay is the full code space address range, 128KB, and is allocated in independent sections of 16KB each, on 16KB boundaries, ranging from the highest address of the actual physical memory space and extending down. Mapping code execution to RAM requires the RAM to have code written into it. Typically, this is done by placing code in a non-volatile memory such as a Flash in the code space. At initialization, the code in the non-volatile memory transfers itself to RAM, maps the appropriate blocks of the code space to the RAM, and then branches to begin execution from RAM. This allows low cost, slow Flash devices to hold an entire code image, which can be executed much faster from RAM. If code is not placed in an external non-volatile memory as described here, it must be transferred to the RAM via the Host Interface. Slow memories are not dynamically sensed. Following reset, the instruction clock operates with a slower cycle while the Flash is copied to RAM. Once code has been copied from Flash to RAM, execution transfers to RAM and the clock is raised to the normal operating frequency. As mentioned above, it is feasible to operate without a code image in a non-volatile memory. In such a system, the 12
firmware must be downloaded to RAM through the host interface before operation can commence. The external SRAM memory must be organized in a 16-bit width to provide adequate performance to implement the 802.11 protocol at 11Mbps rates. Systems designed for lower performance applications may be able to use 8-bit wide memory. The minimum external memory is 128Kbytes of SRAM, organized 8 or 16 bits wide. Typical applications, including 802.11 station designs, use 256Kbytes organized 128K x 16. An access point application could make use of the full address space of the device with 4Mbytes organized a 2M x 16. The ISL3873B supports 8 or 16-bit code space, and 8 or 16-bit data space. Code space is typically populated with the least expensive Flash memory available, usually an 8-bit device. Data space is usually populated with high-speed RAMs configured as a 16-bit space. This mixing of 8/16 bit spaces is fully supported, and may be done in any combination desired for code and data space. The ISL3873B supports direct control of single chip 16-bit wide SRAMs with high/low byte enables, as well as direct control of a 16-bit space constructed from 8-bit wide SRAMs. The type of memory configuration is specified via the appropriate MD pin, sensed when the ISL3873B3873B is reset. ISL3873B pin MUBE-/MA0/MWEH- functions as Address 0 for 8-bit access, (such as Flash) as MWEH (High Byte Write Enable) when two x8 memories are configured as a single x16 space, and as the upper Byte Enable when a single x16 memory is used. No external logic is required to generate the required signals for both types of memory configurations, even when both exist together; all that is required is for the ISL3873B code to configure the ISL3873B memory controller to generate the proper signals for the particular address space being accessed.
ISL3873B
For 8-bit spaces, the ISL3873B dynamically configures pin MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB. MWEL-/MWE- is the only write control, and MOE- is the read output enable. For 16-bit spaces constructed from 8-bit memories, the ISL3873B dynamically configures pin MUBE-/MA0/MWEHcycle-by-cycle as the high byte write enable, MWEL- as the low write enable signal, and MOE- as the read output enable. For 16-bit spaces constructed from single-chip x16 memories (such as SRAMs), the ISL3873B dynamically configures pin MUBE_/MA0/MWEH- cycle-by-cycle as the upper byte enable. Pin MLBE- is connected as the low byte enable, MWEL-/MWE- is the write control, and MOE- is the read output enable. These memory implementations require no external logic. The memory spaces may each be constructed from any type of memory desired. The only restriction is that a single memory space must be constructed from the same type of memory; for example, data space may not use both x8 and x16 memories, it must be all x8, or all x16. This restriction does not apply across memory spaces; e.g., code space may use a x8 memory and data space a single x16 memory, or code space two x8 memories and data space a single x8 memory. set to the defaults used by the standard firmware. During attribute memory accesses HA[9:1] are used. HD[15:0] The host interface is primarily designed for word accesses, although all byte access modes are fully supported. See HCE1-, HCE2- for a further description. Note that attribute memory is specified for and operates with even bytes accesses only. HCE1-, HCE2The PC Card cycle type and width are controlled with the CE signals. Word and Byte wide accesses are supported, using the combinations of HCE1-, HCE2-, and HA0 as specified in the PC Card standard. HWE-, HOEHOE- and HWE- are only used to access attribute memory. Common Memory, as specified in the PC Card standard, is not used in the ISL3873B. HOE- is the strobe that enables an attribute memory read cycle. HWE- is the corresponding strobe for the attribute memory write cycle. The attribute space contains the Card Information Structure (CIS) as well as the Function Configuration Registers (FCR). HIORD-, HIOWRHIORD- and HIOWR- are the enabling strobes for register access cycles to the ISL3873B. These cycles can only be performed once the initialization procedure is complete and the ISL3873B has been put into IO mode. HREGThis signal must be asserted for I/O or attribute cycles. A cycle where HREG- is not asserted will be ignored as the ISL3873B does not support common memory. HINPACKThis signal is asserted by the ISL3873B whenever a valid I/O read cycle takes place. A valid cycle is when HCE1-, HCE2-, HREG-, and HIORD- are asserted, once the initialization procedure is complete. HWAITWait states are inserted in accesses using HWAIT-. The host interface synchronizes all PC Card cycles to the internal ISL3873B clock. The following wait states should be expected: Direct Read or Write to Hardware Register * 1/2 to 1 MCLK assertion of HWAIT- for internal synchronization. Write to Memory Mapped Register, Buffer Access Path, or Attribute Space (Post-Write) * The data required for the write cycle will be latched and therefore only the synchronizing wait state will occur. * Until the queued cycle has actually written to the memory, any subsequent access by the Host will result in a WAIT.
Serial EEPROM Interface
The ISL3873B contains a small on-chip ROM firmware which was added to allow the CIS or CIS plus firmware image to be transferred from an off-chip serial non-volatile memory device to RAM after a system reset. This allows a system configuration without a parallel Flash device. The operating frequency of the serial port is 400kHz with a voltage of 3.3V. Refer to Figure 8 for additional details on configuring the serial memory to the ISL3873B. The Power On Reset Configuration section in this document provides additional details on memory selection and control after a Reset condition.
PC Card Interface
PC Card Physical Interface
The Host interface is compatible to the PC Card 95 Standard (PCMCIA v2.1). The ISL3873B Host Interface pins connect directly to the correspondingly named pins on the PC Card connector with no external components (other than resistors) required. The ISL3873B operates as an I/O card using less than 64 octet locations. Reads and writes to internal registers and buffer memory are performed by I/O accesses. Attribute memory (256 octets) is provided for the CIS table which is located in external memory. Common memory is not used. The following describes specific features of various pins: HA[9:0] Decoding of the system address space is performed by the HCEx-. During I/O accesses HA[5:0] decode the register. HA[9:6] are ignored when the internal HAMASK register is
13
ISL3873B
Read to Attribute Space and Memory Mapped Registers * WAIT will assert until the memory arbitration and access have completed. Buffer Access Paths, BAP0 and BAP1 * An internal pre-read cycle to memory is initiated by a host Buffer Read cycle, after the internal address pointer has auto-incremented. If the next host cycle is a read to the same buffer, the data will be available without a memory arbitration delay. * A single register holds the pre-read data. Thus, any read access to any other memory-mapped register (or the other buffer access path) will result in the pre-read data becoming invalidated. * If another read cycle has invalidated the pre-read, then a memory arbitration delay will occur on the next buffer access path read cycle. HIREQImmediately after reset, the HIREQ- signal serves as the RDY/BSY (per the PC Card standard). Once the ISL3873B firmware initialization procedure is complete, HIREQ- is configured to operate as the interrupt to the PC Card socket controller. Both Level Mode and Pulse Mode interrupts are supported. By default, Level mode interrupts are used, so the interrupt source must be specifically acknowledged or disabled before the interrupt will be removed. RESET When reset is de-asserted, the CIS table is initialized and, once complete, HIREQ- is set high (HIREQ- acts as RDY/BSY from reset and is set high to indicate the card is ready for use). The CIS table resides in Flash memory and is copied to RAM during firmware initialization. The host system can then initialize the card by reading the CIS information and writing to the configuration register. ISA PNP The ISL3873B can be connected to the ISA bus and operate in a Plug and Play environment with an additional chip such as the Fujitsu MB86703, Texas Instruments TL16PNP200A, or Fairchild Semiconductor NM95MS15. See the Application Note AN9874, "ISA Plug and Play with the HFA3841" for more details. Register Interface The logical view of the ISL3873B from the host is a block of 32 word wide registers. These appear in IO space starting at the base address determined by the socket controller. There are three types of registers. Hardware Registers (HW) * 1 to 1 correspondence between addresses and registers. * No memory arbitration delay, data transfer directly to/from registers. * AUX base and offset are write-only, to set up access through AUX data port. 14 Note: All register cycles, including hardware registers, incur a short wait state on the PC Card bus to insure the host cycle is synchronized with the ISL3873B's internal MCLK. Memory Mapped Registers in Data RAM (MM) * 1 to 1 correspondence. * Requires memory arbitration, since registers are actually locations in ISL3873B memory. * Attribute memory access is mapped into RAM as Baseaddress + 0x400. * AUX port provides host access to any location in ISL3873B RAM (reserved). Buffer Access Path (BAP) * No 1 to 1 correspondence between register address and memory address (due to indirect access through buffer address pointer registers). * Auto increment of pointer registers after each access. * Require memory arbitration since buffers are located in ISL3873B memory. * Buffer access may incur additional delay for Hardware Buffer Chaining.
Buffer Access Paths
The ISL3873B has two independent buffer access paths, which permits concurrent read and write transfers. The firmware provides dynamic memory allocation between Transmit and Receive, allowing efficient memory utilization. On-the-fly allocation of (128-byte) memory blocks as needed for reception wastes minimal space when receiving fragments. The ISL3873B hides management of free memory from the driver, and allows fast response and minimum data copying for low latency. The firmware provides direct access to TX and RX buffers based on Frame ID (FID). This facilitates Power Management queuing, and allows dynamic fragmentation and defragmentation by the controller. Simple Allocate/De-allocate commands ensure low host CPU overhead for memory management. Hardware buffer chaining provides high performance while reading and writing buffers. Data is transferred between the host driver and the ISL3873B by writing or reading a single register location (the Buffer Access Path, or BAP). Each access increments the address in the buffer memory. Internally, the firmware allocates blocks of memory as needed to provide the requested buffer size. These blocks may not be contiguous, but the firmware builds a linked list of pointers between them. When the host driver is transferring data through a buffer access path and reaches the end of a physical memory block, hardware in the host interface follows the linked list so that the buffer access path points to the beginning of the next memory block. This process is completely transparent to the host driver, which simply writes or reads all buffer data to the same register. If the host driver attempts to access beyond the end of the allocated buffer, subsequent writes are ignored, and reads will be undefined.
ISL3873B
FID BUFFER MEMORY VIRTUAL FRAME BUFFER
BUFFER DESCRIPTOR ACCESS (FIRMWARE)
ALLOCATE/ DEALLOCATE REQUEST OFFSET CENTER HOST BUS DATA PORT PRE-READ/ POST-WRITE
BLOCK A OFFSET
STATUS
HEADER
D DATA
FIGURE 9. BLOCK DIAGRAM OF A BUFFER ACCESS PATH
USB Port
The USB interface implemented in the ISL3873B complies with the Universal Serial Bus Specification Revision 1.1. dated September 23, 1998, which is available from the USB Implementers' Forum at http://www.usb.org/. The USB supports 4 endpoints. * One Communications Class control endpoint for interface management; * One Communications Class interrupt endpoint for signalling interrupts to the host; and, * Two Bulk endpoints for transfer of encapsulated NDIS functions to and from the host. The USB along with USB support firmware provides an alternate host interface for attaching an 802.11{b} WLAN adapter to a host computer. This interface does not provide "wireless USB" where USB packets are sent on the wireless medium due to timing constraints in the USB protocol. USB+ and USB- are the differential pair signals provided for the user. These signals are capable of directly driving a USB cable. USB_DETECT is a 5V tolerant input to the ISL3873B device. It is used to signal the MAC processor that a USB cable is attached to the unit. Complete details on the USB firmware for controlling this port can be obtained by contacting the factory directly.
last symbol of information has been transmitted while minimizing spurious radiation. To this end, the transmit/receive switch is used to smoothly control the power output. It's also important to apply appropriate modulation to the PA while it is active to minimize radiation of CW signals. Signaling sequences for the beginning and end of normal transmissions are illustrated in Figure 10. Table 1 lists applicable delays associated with these control signals. A transmission begins with PE2 and an internal signal (TX_PE) to the Baseband processor as shown in Figure 10. This enable activates the transmit state machine in the BBP and the upconverter in the ISL3783. This starts the modulated signal flowing to the PA which is turned on by PA_PE once the drive signal is available. The PA power ramps up and the power control loop becomes active and stabilizes. Lastly, the transmit/receive switch is configured for transmission via the differential pair TR_SW and TR_SW_BAR. Delays for these signals related to the initiation of transmission are referenced to PE2. The switching of the T/R switch after the PA is enabled is done to minimize RF spurious radiation. While it is not usual practice to switch the T/R switch while RF is on, in this case it suppresses spurious by employing the 20dB attenuation of the switch until the PA turn-on or turn-off transients have died. After the final data bit has been clocked out of the MAC it waits for an internal control signal (TX_READY) from the Baseband processor. This signals that the BBP has modulated the final information-rich symbol. After allowing time for that symbol to exit the antenna, the MAC de-asserts TR_SW and TR_SW_BAR to shut off transmission and lowers PA_PE followed by PE2 going high. Delays for these signals related to the termination of transmission are referenced to the rising edge of PE2. The baseband processor also internally extends the transmission of data bits for a sufficient time to insure that it outputs the final bits.
Power Sequencing
The ISL3873B provides a number of firmware controlled port pins that are used for controlling the power sequencing and other functions in the front end and baseband processor components of the radio. Packet transmission requires precise control of the radio. Ideally, energy at the antenna ceases immediately after the
15
ISL3873B
PE1
PE2
PA_PE
tD1
tD5
TR_SW
tD3
tD4
TR_SW_BAR
FIGURE 10. TRANSMIT CONTROL SIGNAL SEQUENCING TABLE 1. TRANSMIT CONTROL TIMING SPECIFICATIONS PARAMETER PE2 to PA_PE TPE2 to TR Switch TR Switch to PE2 PA_PE to PE2 SYMBOL tD1 tD3 tD4 tD5 DELAY 0.1 1.5 3 1 TOLERANCE UNITS 0.1 0.1 0.1 0.1 s s s s
Low-Frequency Crystal
The ISL3873B MAC controller can accept the same clock signal as the PHY baseband processor (typically 44MHz), thereby avoiding the need for a separate, MAC-specific oscillator. The ISL3873B input has a low-frequency oscillator. This low-frequency oscillator is intended for use with a 32.768KHz, tuning-fork type watch crystal to permit accurate timekeeping with very low power consumption during sleep state. If a 32.768KHz crystal is connected, the resulting LF clock is supplied to an interval timer to permit measuring sleep intervals as well as providing a programmable wake-up time. In addition, the clock generator can operate either from CLKIN or (very slowly) from the LF clock. Glitch-free switching between these two clock sources, under firmware control, is provided by two, non-architectural Strobe functions ("FAST" and "SLOW"). In addition, during hardware reset, the clock generator source is set to the LF clock if no edges are detected on CLKIN for two cycles of the LF clock (roughly 61 microseconds). This allows proper initialization with omission of either clock source, since without the LF crystal attached there will not be cycles of the LF clock to activate the detection circuit. The ability to initialize the ISL3873B using the LF oscillator to generate MCLK allows the high-frequency (PHY) oscillator to be powered down during sleep state. If this is done, firmware can turn on power to the PHY oscillator upon wake-up, and use the interval timer to measure the start-up and stabilization period before switching to use CLKIN.
PE1 and PE2 encoding details are found in Table 2. Note that during normal receive and transmit operation that PE1 is static and PE2 toggles for receive and transmit states.
TABLE 2. POWER ENABLE STATES PE1 Power Down State Receive State Transmit State PLL Active State PLL Disable State 0 1 1 0 X PE2 0 1 0 1 X PLL_PE 1 1 1 1 0
PLL_PE is controlled via the serial interface, and can be used to disable the internal synthesizer, the actual synthesizer control is an AND function of PLL_PE, and a result of the OR function of PE1 and PE2. PE1 and PE2 will directly control the power enable functionality of the LO buffer(s)/phase shifter.
Master Clock
Prescaler
The ISL3873B contains a clock prescaler to provide flexibility in the choice of clock input frequencies. For 11Mb/s operation, the internal master clock, MCLK, must be at least 11MHz. The clock generator itself requires an input from the prescaler that is twice the desired MCLK frequency. Thus the lowest oscillator frequency that can be used for an 11MHz MCLK is 22MHz. The prescaler can divide by integers and 1/2 steps (IE 1, 1.5, 2, 2.5). Another way to look at it is that the divisor ratio between the external clock source and the internal MCLK may be integers between 2 and 14. Typically, the 44MHz baseband clock is used as the input, and the prescaler is set to divide by 2. Contact the factory for further details on setting the clock prescaler register in the ISL3873B. 16
Clock Generator
The ISL3873B can operate with MCLK frequencies up to at least 12MHz and CLKIN frequencies of at least 50MHz. The MCLK prescaler generates MCLK (and QCLK) from the external clock provided at the CLKIN input, or from the output of the LF oscillator. The MCLK prescaler divides the selected input clock by any integer value between 2 and 16, inclusive. * When using a 44MHz CLKIN, as is typical for 802.11 or 802.11b controllers with a PC Card Host Interface, common divisors are 4 (11MHz) or 5 (8.8MHz)
ISL3873B
* When using a 48MHz CLKIN, as is typical for 802.11 or 802.11b controllers with a USB host interface, common divisors are 4 (12MHz) or 6 (8MHz) The MCLK prescaler is set to divide by 16 at hardware reset to allow initialization firmware to be executed from slow memory devices at any CLKIN frequency. The MCLK prescaler generates glitch free output when the divisor is changed. This allows firmware to change the MCLK frequency during operation, which is especially useful to selectively reduce operating speed, thereby conserving power, when full speed processing is not required.
22pF XTALIN X1 XTALOUT 4700pF 10M C2 C1
Power On Reset Configuration
Power On Reset is issued to the ISL3873B with the RESET pin or via the soft reset bit, SRESET, in the Configuration Option Register (COR, bit 7). RESET originates from the HOST system which applies RESET for at least 0.01ms after VCC has reached 90% of its end value (see PC-Card standard, Vol. 2, Ch. 4.12.1). The MD[15:8] pin values are sampled during RESET or Software Reset (SRESET). These pins have internal 50K resistors. External pull-up or pull-down resistors (typically 10k) are used for bits which need to be configured differently than the default. Table 3 summarizes the effect per pin. Table 4 provides the MD15 and MD14 bit values required to allow the ISL3873B to use Serial EEPROM option. MD[11], StrIdle, has no equivalent functionality in any control register. When asserted at reset, it will inhibit firmware execution. This is used to allow the initial download of firmware in "Genesis Mode". See the Hardware Reference Manual for more details. The latch is cleared when the Software Reset, SRESET, COR(7) is active.
FIGURE 11. 32.768kHz CRYSTAL
TABLE 3. INITIALIZATION STRAPPING OPTIONS ON MBUS DATA PINS BITS NAME DEFAUL T 30 FUNCTION Indicates type of serial NV memory to be read by initialization firmware in on-chip ROM. Up to 8 NV device types can be encoded with (StrIdle or NVtype). If StrIdle = 0, NV memory holds a firmware image, and NVtype identifies 1 of 4 "large" (. = 128Kb) types. If StrIdle = 1, the NV memory just holds the CIS, and NVtype identifies 1 of 4 "small" (< = 8Kb) types. Use the Serial Host Interface (USB), and disable all PC Card functions except attribute space, for access to the COR and HCR for firmware debugging support. When = 0, use the Parallel Host Interface (PC Card or ISA). Use 4-wire interface to SRAM (CS-, OE-, WEH-, WEL-) the ISL3873B x8 SRAMs. When = 0 selects 5-wire interface for use with x16 SRAM (CS-, OE-, WE-, UBE-, LBE-). Start idle (wait for download from PC Card host interface). RAM and NV space at startup is x 16. When = 0 RAM and NV space at startup is x 8. If starting from off-chip NV memory this setting must indicate the width of the startup Flash Memory. During initialization, firmware can set separate widths or RAM and NV space in the Memory Control Register. Disable mapping of off-chip control store to NV space (hence map off-chip control store to RAM space). When = 0 off-chip control store is mapped to NV memory Disable on-chip control store ROM. When = 0 enable on-chip control store ROM. Set host interface control signals and address decoding for PC card. When = 1 set host interface signals and address decoding is for ISA bus, with all registers in I/O space and attribute space disabled. To use ISA mode, PHIenable must be = 1 to enable a parallel host interface. Enable I/O space decoding for the physical FCRs. When = 1, the COR, CSR, and PRR registers are accessible at I/O space offsets 0x40, 0x42, and 0x44 respectively. When = 0 these registers are only accessible in attribute space. This bit is ignored when PHIenable = 0, and is overridden (forced = 1) when ISAmode =1. FCRinIO = 1 is useful for PC Card operation (PHIenable = 1, ISAmode = 0) to allow non-OS software to access the COR/HCR in OS environments where the system software does not permit application software to access attribute space.b Not assigned.
15:14 NVtype[1:0]
13 12 11 10
SHIenable 4Wire StrIdle Mem16
0 1 0 0
9 8 7
NVds ROMds ISAmode
0 1 0
6
FCRinIO
0
5:0
Spare
0 x 00
a. FCRinIO = 1 forces HAMASK [0] = 1 to expand I/O space decoding from 0 x 40 to 0 x 80 bytes. TABLE 4. SERIAL EEPROM SELECTION MD15 0 0 1 MD14 0 1 X DEVICE TYPE AT45DB011 24C08 (Note) None FUNCTION Large Serial Device used to transfer firmware to SRAM Small Serial Device which contains only CIS. MAC goes idle after loading CIS and waits for host. Modes not supported in firmware at this time. Consult factory for additional device types added.
NOTE: The operating frequency of the serial port is 400kHz with a voltage of 3.3V.
17
ISL3873B Baseband Processor
The Baseband Processor operation is controlled by the ISL3873B firmware. Detailed information on programming the Baseband Processor can be obtain by contacting the factory. BBP Packet Reception The receive demodulator scrutinizes I and Q for packet activity. When a packet arrives at a valid signal level the demodulator acquires and tracks the incoming signal. It then sifts through the demodulator data for the Start Frame Delimiter (SFD). After SFD is detected, the BBP picks off the needed header fields from the real-time demodulated bitstream. Assuming all is well with the header, the BBP decodes the signal field in the header and switches to the appropriate data rate. If the signal field is not recognized, or the CRC16 is in error, the demodulator will return to acquisition mode looking for another packet. If all is well with the header, and after the demodulator has switched to the appropriate data rate, then the demodulator will continue to provide data to the MAC in the ISL3873B indefinitely. of the receiver when it is needed most at low signal level. At IF, the gain control is linear and covers the bulk of the gain control range of the receiver. The AGC loop is partially digital which allows for holding the gain fixed during a packet. The AGC sensing mechanism uses a combination of the I and Q A/D converters and the detected signal level in the IF to determine the gain settings. The A/D outputs are monitored and controlled in the ISL3873B for the desired nominal level.
RX_AGC_IN Interface
The signal level in the IF stage is monitored to determine when to impose the 30dB gain reduction in the RF stage. This maximizes the dynamic range of the receiver by keeping the RF stages out of saturation at high signal levels. When the IF circuits' sensor output reaches 0.5V DD , the ISL3873B comparator switches in the 30dB pad and also adds 30dB of gain to the IF AGC amplifier. This compensates the IF AGC and RSSI measures.
TX I/Q DAC Interface
The transmit section outputs balanced differential analog signals from the transmit DACs to the HFA3783. These are DC coupled and digitally filtered.
RX I/Q A/D Interface
The PRISM baseband processor chip (ISL3873B) includes two 6-bit Analog to Digital converters (A/Ds) that sample the balanced differential analog input from the IF down converter device (HFA3783). The I/Q A/D clock, samples at twice the chip rate with a nominal sampling rate of 22MHz. The interface specifications for the I and Q A/Ds are listed in Table 5. The ISL3873B is designed to be DC coupled to the HFA3783.
TABLE 5. I, Q, A/D SPECIFICATIONS PARAMETER Full Scale Input Voltage (VP-P ) Input Bandwidth (-0.5dB) Input Capacitance (pF) Input Impedance (DC) fS (Sampling Frequency) MIN 0.90 5k TYP 1.00 11MHz 2 22MHz MAX 1.10 -
Transmitter Description
The ISL3873B transmitter is designed as a Direct Sequence Spread Spectrum Phase Shift Keying (DSSS PSK) modulator which is capable of handling data rates of up to 11Mbps (refer to AC and DC specifications). The various modes of the modulator are Differential Binary Phase Shift Keying (DBPSK) for 1Mbps, Differential Quaternary Phase Shift Keying (DQPSK) for 2Mbps, and Complementary Code Keying (CCK) for 5.5Mbps and 11Mbps. CCK is essentially a quadra-phase form of M-ARY Keying. A description of that modulation can be found in Chapter 5 of: "Telecommunications System Engineering", by Lindsey and Simon, Prentiss Hall publishing. The formula for CCK can be found later in this datasheet. The implemented data rates using a clock rate of 44MHz are shown in Table 6 and the modulation schemes are indicated in Figure 13. The major functional blocks of the transmitter include a Processor Interface, Modulator, Data Scrambler, Preamble/Header Generator, TX Filter, AGC Control, and ADC and DAC circuits. Figure 17 provides a basic block diagram of the DSSS Baseband Processor with an emphasis on the transmitter section. Figure 19 provides a basic block diagram of the DSSS Baseband Processor with an emphasis on the receive section. The preamble is always transmitted as the DBPSK waveform while the header can be configured to be either DBPSK, or DQPSK, and data packets can be configured for DBPSK, DQPSK, or CCK. The preamble is used by the receiver to
The voltages applied to pin 16, VREF and pin 21, IREF set the references for the internal I and Q A/D converters. In addition, For a nominal I/Q input of 400mV P-P , the suggested VREF voltage is 1.2V.
AGC Circuit
The AGC circuit as shown in Figure 12 is designed to adjust for signal level variations and optimize A/D performance for the I and Q inputs by maintaining the proper headroom on the 6-bit converters. There are two gain stages being controlled. At RF, the gain control is a 30dB step change. This RF gain control optimizes the receiver dynamic range when the signal level is high and maintains the noise figure 18
ISL3873B
achieve initial Pseudo Noise (PN) synchronization while the header includes the necessary data fields of the communications protocol to establish the physical layer link. The transmitter generates the synchronization preamble and header and knows when to make the DBPSK to DQPSK or CCK switchover, as required. For the 1 and 2Mbps modes, the transmitter accepts data from the external source, scrambles it, differentially encodes it as either DBPSK or DQPSK, and spreads it with the BPSK PN sequence. The baseband digital signals are then output to the external IF modulator. For the CCK modes, the transmitter inputs the data and partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps, it uses four of those bits to select one of 16 complex spread sequences from a table of CCK sequences. Thus, there are 16 possible spread sequences to send, but only one is sent. This sequence is then modulated on the I and Q outputs. The initial phase reference for the data portion of the packet is the phase of the last bit of the header. At 11Mbps, one byte is used as above where 8 bits are used to select one of 256 spread sequences for a symbol. Bit rates for the ISL3873B are defined in Table 6. This table provides information on bit rates, data rates and symbol rates for an MCLK of 44MHz clock. Figure 13 shows the modulation schemes for the different bits rates. The modulator is completely independent from the demodulator, allowing the PRISM baseband processor to be used in full duplex operation.
Header/Packet Description
The ISL3873B is designed to handle packetized Direct Sequence Spread Spectrum (DSSS) data transmissions. The ISL3873B generates its own preamble and header information. It uses two packet preamble and header configurations. The first is backwards compatible with the existing IEEE 802.11-1997 1 and 2Mbps modes and the second is the optional shortened mode which maximizes throughput at the expense of compatibility with legacy equipment. In the long preamble mode, the device uses a synchronization preamble of 128 symbols along with a header that includes four fields. The preamble is all 1's (before entering the scrambler) plus a Start Frame Delimiter (SFD). The actual transmitted pattern of the preamble is randomized by the scrambler. The preamble is always transmitted as a DBPSK waveform (1Mbps). The duration of the long preamble and header is 192s. In the short preamble mode, the modem uses a synchronization field of 56 zero symbols along with an SFD transmitted at 1Mbps. The short header is transmitted at the 2Mbps rate. The synchronization preamble is all 0's to distinguish it from the long header mode and the short preamble SFD is the time reverse of the long preamble SFD. The duration of the short preamble and header is 96s.
Start Frame Delimiter (SFD) Field (16 Bits)
This field is used to establish the link frame timing. The ISL3873B will not declare a valid data packet, even if it PN acquires, unless it detects the SFD. The ISL3873B receiver auto-detects if the packet is long or short preamble and sets SFD time-out. The timer starts counting after initialization of the de-scrambler is complete.
RX_RF_AGC RX_IF_DET RX_IF_AGC RX_I I ADC HFA3683 HFA3783 RX_Q Q ADC THRESH. DETECT IF DAC
1 1 7 AGC CTL
6 6 DEMOD
DATA I/O I/O ISL3873B
FIGURE 12. AGC CIRCUIT TABLE 6. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz DATA MODULATION DBPSK DQPSK CCK CCK A/D SAMPLE CLOCK (MHz) 22 22 22 22 TX SETUP CR 5 BITS 1, 0 00 01 10 11 RX SIGNAL CR 63 BITS 7, 6 00 01 10 11 DATA RATE (Mbps) 1 2 5.5 11 SYMBOL RATE (MSPS) 1 1 1.375 1.375
19
ISL3873B
802.11 DSSS BPSK 1Mbps BARKER DATA
802.11 DSSS QPSK 2Mbps BARKER
5.5Mbps CCK COMPLEX SPREAD FUNCTIONS
11Mbps CCK COMPLEX SPREAD FUNCTIONS
1 BIT ENCODED TO ONE OF 2 CODE WORDS (TRUE-INVERSE)
2 BITS ENCODED TO ONE OF 4 CODE WORDS
4 BITS ENCODED TO ONE OF 16 COMPLEX CCK CODE WORDS
8 BITS ENCODED TO ONE OF 256 COMPLEX CCK CODE WORDS
IOUT QOUT 11 CHIPS CHIP RATE SYMBOL RATE 11 MC/S 1 MS/S 11 CHIPS 11 MC/S 1 MS/S 8 CHIPS 11 MC/S 1.375 MS/S 8 CHIPS 11 MC/S 1.375 MS/S
I vs. Q
FIGURE 13. MODULATION MODES
PREAMBLE (SYNC) 128/56 BITS Start FRAME DELIMITER 16 BITS SIGNAL FIELD 8 BITS SERVICE FIELD 8 BITS LENGTH FIELD 16 BITS CRC16 16 BITS
PREAMBLE
HEADER
FIGURE 14. 802.11 PREAMBLE/HEADER
Header Field
The header field is defined by four fields which are shown in Figure 14. These fields are Signal Field, Service Field, Length Field and CITT-CRC16 Field. They are further defined by the following: Signal Field (8 Bits) - This field indicates what data rate the data packet that follows the header will be. The ISL3873B receiver looks at the signal field to determine whether it needs to switch from DBPSK demodulation into DQPSK, or CCK demodulation at the end of the preamble and header fields. Service Field (8 Bits) - The MSB of this field is used to indicate the correct length when the length field value is ambiguous at 11Mbps. See IEEE STD 802.11 for definition of the other bits. Bit 2 is used by the ISL3873B to indicate that the carrier reference and the bit timing references are derived from the same oscillator (locked oscillators). Length Field (16 Bits) - This field indicates the number of microseconds it will take to transmit the payload data (PSDU). The external controller (MAC) will check the length field in determining when it needs to de-assert RX_PE.
CCITT - CRC 16 Field (16 Bits) - This field includes the 16-bit CCITT - CRC 16 calculation of the three header fields. This value is compared with the CCITT - CRC 16 code calculated at the receiver. The ISL3873B receiver will indicate a CCITT - CRC 16 error via CR24 bit 2 and will lower MD_RDY and reset the receiver to the acquisition mode if there is an error. The CRC or cyclic Redundancy Check is a CCITT CRC-16 FCS (Frame Check Sequence). It is the ones complement of the remainder generated by the modulo 2 division of the protected bits by the polynomial: x16 + x12 + x5 + 1 The protected bits are processed in transmit order. All CRC calculations are made ahead of data scrambling. A shift register with two taps is used for the calculation. It is preset to all ones and then the protected fields are shifted through the register. The output is then complemented and the residual shifted out MSB first. The following Configuration Registers (CR) are used to program the preamble/header functions, more programming details about these registers can be found in the Control Registers section of this document:
20
ISL3873B
CR 3 - Defines the short preamble length minus the SFD in symbols. The 802.11 protocol requires a setting of 56d = 38h for the optional short preamble. CR 4 - Defines the long preamble length minus the SFD in symbols. The 802.11 protocol requires a setting of 128d = 80h for the mandatory long preamble. CR 5 Bits 0, 1 - These bits of the register set the Signal field to indicate what modulation is to be used for the data portion of the packet. CR 6 - The value to be used in the Service field. CR 7 and 8 - Defines the value of the transmit data length field. This value includes all symbols following the last header field symbol and is in microseconds required to transmit the data at the chosen data rate. The packet consists of the preamble, header and MAC Protocol Data Unit (MPDU). The data is transmitted exactly as received from the control processor. Some dummy bits will be appended to the end of the packet to ensure an orderly shutdown of the transmitter. This prevents spectrum splatter. At the end of a packet, the external controller is expected to deassert the TX_PE line to shut the transmitter down. desired DBPSK coding by differential encoding the serial data from the scrambler and driving both the I and Q output channels together. For the 2Mbps DQPSK data rate and for the header in the short preamble mode, the data coder implements the desired coding as shown in the DQPSK Data Encoder Table 7. This coding scheme results from differential coding of dibits (2 bits). Vector rotation is counterclockwise although bits 6 and 7 of configuration register CR 1 can be used to reverse the rotation sense of the TX or RX signal if desired.
Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and CCK spread spectrum signals. The modulator is capable of automatically switching its rate where the preamble is DBPSK modulated, and the data and/or header are modulated differently. The modulator can support date rates of 1, 2, 5.5 and 11Mbps. Quadraphase (I/Q) modulation is used at the baseband for all modulation modes. Further information on the programming details required to set up the modulator can be obtained by contacting the factory.
TABLE 7. DQPSK DATA ENCODER PHASE SHIFT 0 +90 +180 -90 DIBIT PATTERN (d0, d1) d0 IS FIRST IN TIME 00 01 11 10
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the scrambling algorithm specified in the IEEE 802.11 standard. This scrambler is used for the preamble, header, and data in all modes. The data scrambler is a self synchronizing circuit. It consists of a 7-bit shift register with feedback from specified taps of the register. Both transmitter and receiver use the same scrambling algorithm. The scrambler can be disabled by setting CR32 bit 2 to 1.
NOTE: Be advised that the IEEE 802.11 compliant scrambler in the ISL3873B has the property that it can lock up (stop scrambling) on random data followed by repetitive bit patterns. The probability of this happening is 1/128. The patterns that have been identified are all zeros, all ones, repeated 10s, repeated 1100s, and repeated 111000s. Any break in the repetitive pattern will restart the scrambler. To ensure that this does not cause any problem, the CCK waveform uses a ping pong differential coding scheme that breaks up repetitive 0's patterns.
In the 1Mbps DBPSK mode, the I and Q Channels are connected together and driven with the output of the scrambler and differential encoder. The I and Q Channels are then both multiplied with the 11-bit Barker word at the spread rate. The I and Q signals go to the Quadrature upconverter (HFA3724) to be modulated onto a carrier. Thus, the spreading and data modulation are BPSK modulated onto the carrier. For the 2Mbps DQPSK mode, the serial data is formed into dibits or bit pairs in the differential encoder as detailed above. One of the bits from the differential encoder goes to the I Channel and the other to the Q Channel. The I and Q Channels are then both multiplied with the 11-bit Barker word at the spread rate. This forms QPSK modulation at the symbol rate with BPSK modulation at the spread rate.
Scrambling is done by division with a prescribed polynomial as shown in Figure 15. A shift register holds the last quotient and the output is the exclusive or of the data and the sum of taps in the shift register. The transmit scrambler seed for the long preamble or for the short preamble can be set with CR48 or CR49.
SERIAL DATA OUT Z-1 Z-2 Z-3 Z-4 XOR Z-5 Z-6 Z-7
CCK Modulation
For the CCK modes, the spreading code length is 8 complex chips and based on complementary codes. The chipping rate is 11Mchip/s. The following formula is used to derive the CCK code words that are used for spreading both 5.5 and 11Mbps:
c= -e e
j ( 1 + 2 + 3 + 4 )
FIGURE 15. SCRAMBLING PROCESS
,e
,e
, -e
,e
For the 1Mbps DBPSK data rates and for the header in all rates using the long preamble, the data coder implements the
(LSB to MSB), where c is the code word.
21

j( + ) 1 4

SERIAL DATA IN XOR
,e
j ( 1 + 3 + 4 ) j ( + ) 1 3
,e
j ( 1 + 2 + 4 ) j ( + ) 1 2 j
,
j( + + ) 1 2 3
1
ISL3873B
The terms: 1, 2, 3, and 4 are defined below for 5.5Mbps and 11Mbps. This formula creates 8 complex chips (LSB to MSB) that are transmitted LSB first. The coding is a form of the generalized Hadamard transform encoding where the phase 1 is added to all code chips, 2 is added to all odd code chips, 3 is added to all odd pairs of code chips and 4 is added to all odd quads of code chips. The phase 1 modifies the phase of all code chips of the sequence and is DQPSK encoded for 5.5 and 11Mbps. This will take the form of rotating the whole symbol by the appropriate amount relative to the phase of the preceding symbol. Note that the last chip of the symbol defined above is the chip that indicates the symbol's reference phase. For the 5.5Mbps CCK mode, the output of the scrambler is partitioned into nibbles. The first two bits are encoded as differential symbol phase modulation in accordance with Table 8. All odd numbered symbols of the MPDU are given an extra 180 degree () rotation in addition to the standard DQPSK modulation as shown in the table. The symbols of the MPDU shall be numbered starting with "0" for the first symbol for the purposes of determining odd and even symbols. That is, the MPDU starts on an even numbered symbol. The last data dibit (d2 and d3) CCK encodes the chips as specified in Table 9. This table is derived from the CCK formula above by setting 2 = (d2*pi)+ pi/2, 3 = 0, and 4 = d3*pi. In Table 9 d2 and d3 are in the order shown and the complex chips are shown LSB to MSB (left to right) with LSB transmitted first.
TABLE 8. DQPSK ENCODING TABLE EVEN SYMBOLS ODD SYMBOLS DIBIT PATTERN (d(0), d(1)) PHASE CHANGE PHASE CHANGE (+j) d(0) IS FIRST IN TIME (+j) 00 01 11 10 0
given an extra 180 degree () rotation in accordance with the DQPSK modulation as shown in Table 8. Symbol numbering starts with "0" for the first symbol of the MPDU. The data dibits: (d2, d3), (d4, d5), (d6, d7) encode 2, 3, and 4 respectively based on QPSK as specified in Table 10. Note that this table is binary, not grey, coded.
Transmit Filter Description
To minimize the requirements on the analog transmit filtering, the transmit section shown in Figure 17 has an output digital filter. This filter is a Finite Impulse Response (FIR) style filter whose passband shape is set by tap coefficients. This filter shapes the spectrum to meet the radio spectral mask requirements while minimizing the peak to average amplitude on the output. To meet the particular spread spectrum processing gain regulatory requirements in Japan on channel 14, an extra FIR filter shape has been included that has a wider main lobe. This increases the 90% power bandwidth from about 11MHz to 14MHz. It has the unavoidable side effect of increasing the amplitude modulation, so the available transmit power is compromised by 2dB when using this filter (CR 11 bit 5).
TABLE 10. QPSK ENCODING TABLE DIBIT PATTERN (d(i), d(i+1)) d(i) IS FIRST IN TIME 00 01 10 11 PHASE 0
/2
3/2 (-/2)
TX Power Control
The transmitter power can be controlled via two registers. The first register, CR58, contains the results of power measurements digitized by the ISL3873B. By comparing this measurement to what is needed for transmit power, a determination is made whether to raise or lower the transmit power. It does this by writing the power level desired to register CR31.
3/2 (-/2) 0
/2
3/2 (-/2)
/2
TABLE 9. 5.5Mbps CCK ENCODING TABLE d2, d3 00 01 10 11 1j -1j -1j 1j 1 -1 1 -1 1j -1j -1j 1j CHIPS -1 1 -1 1 1j 1j -1j -1j 1 1 1 1 -1j -1j 1j 1j 1 1 1 1
Clear Channel Assessment (CCA) and Energy Detect (ED) Description
The Clear Channel Assessment (CCA) circuit implements the carrier sense portion of a Carrier Sense Multiple Access (CSMA) networking scheme. The Clear Channel Assessment (CCA) monitors the environment to determine when it is clear to transmit. The CCA circuit in the ISL3873B can be programmed to be a function of RSSI (energy detected on the channel), CS1, SQ1, or various combinations. The CCA is used by the Media Access Controller (MAC) in the ISL3873B. The MAC decides on transmission based on traffic to send and the CCA indication. The CCA indication can be ignored, allowing transmissions independent of any channel conditions. The CCA in combination with the visibility of the various internal parameters (i.e., Energy detection
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted per symbol. The first dibit (d0, d1) encodes the phase 1 based on DQPSK. The DQPSK encoder is specified in Table 8 above. The phase change for 1 is relative to the phase 1 of the preceding symbol. In the case of rate change, the phase change for 1 is relative to the phase 1 of the preceding CCK symbol. All odd numbered symbols of the MPDU are
22
ISL3873B
measurement results), can assist the MAC in executing algorithms that can adapt to the environment. These algorithms can increase network throughput by minimizing collisions and reducing transmissions liable to errors. There are three measures that can be used in the CCA assessment. The Receive Signal Strength Indication (RSSI) which indicates the energy at the antenna, CS1 and carrier sense (SQ1). CS1 becomes active anytime the AGC portion of the circuit becomes unlocked, which is likely at the onset of a signal that is strong enough to support 11Mbps, but may not occur with the onset of a signal that is only strong enough to support 1 or 2MBps. CS1 stays active until the AGC locks and a SQ1 assessment is done, if SQ1 is false, then CS1 is cleared, which deasserts CCA. If SQ1 is true, then tracking is begun, and CCA continues to show the channel busy. CS1 may occur at any time during acquisition as the AGC state machine runs asynchronously with respect to slot times. SQ1 becomes active only when a spread signal with the proper PN code has been detected, and the peak correlation amplitude to sidelobe ratio exceeds a set threshold, so it may not be adequate in itself. A SQ1 evaluation occurs whenever the AGC has remained locked for the entire data ingest period. When this happens, SQ1 is updated between 8 and 9s into the 10s dwell. If CS1 is not active, two consecutive SQ1's are required to advance the part to tracking. The state of CCA is not guaranteed from the time RX_PE goes high until the first CCA assessment is made. At the end of a packet, after RXPE has been deasserted, the state of CCA is also not guaranteed. The Receive Signal Strength Indication (RSSI) measurement is derived from the state of the AGC circuit. ED is the comparison result of RSSI against a threshold. The threshold may be set to an absolute power value, or it may be set to be N dB above the measured noise floor. See CR 35. The ISL3873B measures and stores the RSSI level when it detects no presence of BPSK or QPSK signals. The average value of a 256 value buffer is taken to be the noise floor. Thus, the value of the noise floor will adapt to the environment. A separate noise floor value is maintained for each antenna. An initial value of the noise floor is established within 50s of the chip being active and is refined as time goes on. Deasserting RX_PE does not corrupt the learned values. If the absolute power metric is chosen, this threshold is normally set to between -70 and -80dBm. If desired, ED may be used in the acquisition process as well as CCA. ED may be used to mask (squelch) weak signals and prevent radio reception of signals too weak to support the high data rates, signals from adjacent cells, networks, or buildings. See CR 47 (bit 6). The Configuration registers effecting the CCA algorithm operation are summarized below (more programming details on these registers can be found under the Control Registers section of this document). The CCA output from pin 60 of the device can be defined as active high or active low through CR 1 (bit 2). CR9(6:5) allows CCA to be programmed to be a function of ED only, the logical operation of (CS1 OR SQ1), the logical function of (ED AND (CS1 OR SQ1)), or (ED OR (CS1 OR SQ1)). CR9(7) lets the user select from sampled CCA mode, which means CCA will not glitch, is updated once per symbol and is valid for reading at 15.8s or 18.7s. In non-sampled mode, CCA may change at any time, potentially several times per slot, as ED and CS1 operate asynchronously to slot times. In a typical system CCA will be monitored to determine when the channel is clear. Once the channel is detected busy, CCA should be checked periodically to determine if the channel becomes clear. Once MD_RDY goes active, CCA should be ignored for the remainder of the message. Failure to monitor CCA until MD_RDY goes active (or use of a timeout circuit) could result in a stalled system as it is possible for the channel to be busy and then become clear without an MD_RDY occurring.
AGC Description
The AGC system consists of the 3 chips handling the receive signal, the RF to IF down-converter HFA3683, the IF to baseband converter HFA3783, and the baseband processor (BBP) section of the ISL3873B. The AGC loop (Figure 12) is digitally controlled by the BBP. Basically it operates as follows: Initially, the receiver is set for high gain. The percent of time that the A/D converters in the baseband processor are saturated is monitored along with signal amplitude and the gain is adjusted down until the amplitude is what will optimize the demodulator's performance. If the amount of saturation is great, the initial gain adjust steps are large. If the signal overload is small, they are less. When the gain is about right and the A/Ds' outputs are within the lock window (CR19), the BBP declares AGC lock and stops adjusting for the duration of the packet. If the signal level then varies more than a preset amount (CR20, CR29), the AGC is declared unlocked and the gain again allowed to readjust. The BBP looks for the locked state following an unlocked state (CS1) as one indication that a received signal is on the antenna. This starts the receive process of looking for PN correlation (SQ1). Once PN correlation and AGC lock are found, the processor begins acquisition. For large signals, the power level in the RF stage output is also monitored and if it is large, the LNA stage is shut down. This removes 30dB of gain from the receive chain which is compensated for by replacing 30dB of gain in the IF AGC stage. There is some hysteresis in this operation and once the AGC locks, it is locked as well. This improves the receiver dynamic range.
23
ISL3873B RX_RF_AGC Pad Operation
30dB Pad Engaging (RF Chip Low Gain):
If the AGC is not locked onto a packet, a '1' on the ifCompDet input will engage in the 30dB attenuation pad. This causes the AGC to go out of lock and also forces the attenuation accumulator to be set to the programmed value of CR27. The AGC then attempts to lock on the signal. If the AGC is locked on a packet, ifCompDet is ignored. 30DB PAD RELEASING (RF CHIP HIGH GAIN): If the AGC is not locked onto a packet and the attenuation accumulator sum falls below the programmable threshold (CR27), the pad will release. This is for the case where a noise spike kicked in the 30dB pad and the pad should release when the noise spike ends. Since the noise floor is different for different environments, it is possible that in some cases CR27's programmed value will be below the noise floor and the pad will not be removed except by RXPE going low. There is a recommended value to program CR27 (24dB), but that depends on what environment the radio is in. During a packet (after AGC lock), the 30dB pad is held constant and the CR27 threshold is ignored. RXPE low forces the pad to release whether in the middle of a packet or not. At the end of a packet, RXPE always goes low, forcing the pad to release. Notes: The attenuation accumulator is basically about equal to the current RSSI value. The accumulator output, after going through the interpolator lookup table, feeds the AGC D/A. The value used to represent the pad is programmable (CR17), but is recommended to be set to 30dB. ifCompDet is a signal from the HFA3783 chip. A '1' indicates its inputs are near saturation and it needs the RF chip to switch from high gain to low gain. RX_IF_Det is the input to the ISL3873B chip which is connected to ifCompDet on the HFA3783. RX_RF_AGC is the output of the ISL3873B chip and '1' is high gain, '0' is low gain. relatively wide loop bandwidth which is then stepped down as the packet progresses. Coherent processing improves the BER performance margin as opposed to differentially coherent processing for the CCK data rates. The baseband processor uses time invariant correlation to strip the Barker code spreading and phase processing to demodulate the resulting signals in the header and DBPSK/DQPSK demodulation modes. These operations are illustrated in Figure 18 which is an overall block diagram of the receiver processor. In processing the DBPSK header, input samples from the I and Q A/D converters are correlated to remove the spreading sequence. The peak position of the correlation pulse is used to determine the symbol timing. The sample stream is decimated to the symbol rate and corrected for frequency offset prior to PSK demodulation. Phase errors from the demodulator are fed to the NCO through a lead/lag filter to maintain phase lock. The carrier is de-rotated by the carrier tracking loop. The demodulated data is differentially decoded and descrambled before being sent to the header detection section. In the 1Mbps DBPSK mode, data demodulation is performed the same as in header processing. In the 2Mbps DQPSK mode, the demodulator demodulates two bits per symbol and differentially decodes these bit pairs. The bits are then serialized and descrambled prior to being sent to the output. In the CCK modes, the receiver removes carrier frequency offsets and uses a bank of correlators to detect the modulation. A biggest picker finds the largest correlation in the I and Q Channels and determines the sign of those correlations. For this to happen, the demodulator must know the starting phase which is determined by referencing the data to the last bit of the header. Each symbol demodulated determines 1 or 2 nibbles of data. This is then serialized and descrambled before being passed to the output. Carrier tracking is via a lead/lag filter using a digital Costas phase detector. Chip tracking in the CCK modes is chip decision directed or slaved to the carrier tracking depending on whether or not the locked oscillator design is utilized in the radio.
Acquisition Description
A projected worst case time line for the acquisition of a signal with a short preamble and header is shown. The synchronization part of the preamble is 56 symbols long followed by a 16-bit SFD. The receiver must monitor the antenna to determine if a signal is present. The timeline is broken into 10s blocks (dwells) for the scanning process. This length of time is necessary to allow enough integration of the signal to make a good acquisition decision. This worst case time line example assumes that the signal arrives part way into the first dwell such as to just barely catch detection. The signal and the scanning process are asynchronous and the signal could start anywhere. In this timeline, it is assumed that the signal is present in the first 10s dwell, but was missed due to power amplifier ramp up.
Demodulator Description
The receiver portion of the baseband processor, performs A/D conversion and demodulation of the spread spectrum signal. It correlates the PN spread symbols, then demodulates the DBPSK, DQPSK, or CCK symbols. The demodulator includes a frequency tracking loop that tracks and removes the carrier frequency offset. In addition, it tracks the symbol timing, and differentially decodes and descrambles the data. The data is output through the RX Port to the external processor. The PRISM baseband processor in the ISL3873B uses coherent demodulation. The ISL3873B is designed to achieve rapid settling of the carrier tracking loop during acquisition. Rapid phase fluctuations are handled with a 24
ISL3873B
TX POWER RAMP 56 SYMBOL SYNC 2 20 SYMBOLS AGC SETTLE AND LOCK AND INITIAL DETECTION 20 SYMBOLS VERIFY AND CIR/FREQUENCY ESTIMATION AND CMF/NCO JAMMING 7 SYM
SFD
16 SYMBOLS
SEED DESCRAMBLER START SFD SEARCH
SFD DET START DATA
FIGURE 16. ACQUISITION TIMELINE, NON DIVERSITY
VDDA (ANALOG) IREF
GND (ANALOG)
VDD (DIGITAL)
GND (DIGITAL)
OUTPUT MUX
TEST CONTROL
VREF TX_AGC_IN 6-BIT ADC TX AGC CONTROL TX_IF_AGC ANTSEL ANTSEL REGISTER 6-BIT DAC
TXI+/DAC
OUTPUT MUX
TXQ+/DAC INTERNAL SIGNALS TRANSMIT PORT
TRANSMIT FILTER PREAMBLE/HEADER CRC-16 GENERATOR
TX_RDY TXCLK
MODULATOR, BARKER/CCK
TX_DATA SCRAMBLER
TXD RXCLK PROCESSOR INTERFACE
TX STATE CONTROL TIMING GENERATOR MCLK
CCA
MAC CONTROL SIGNALS
TX_PE
MCLK
FIGURE 17. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
Meanwhile signal quality and signal frequency measurements are made simultaneous with symbol timing measurements. A CS1 followed by SQ1 active, or two consecutive SQ1s will cause the part to finish the acquisition phase and enter the tracking phase. Prior to initial acquisition the NCO is inactive (0Hz) and carrier phase measurement are done on a symbol by symbol basis. After acquisition, coherent DPSK demodulation is in effect. After a brief setup time as illustrated on the timeline, the signal begins to emerge from the demodulator.
It takes 7 more symbols to seed the descrambler before valid data is available. This occurs in time for the SFD to be received. At this time the demodulator is tracking and in the coherent PSK demodulation mode so it will no longer acquire new signals. If a much larger signal overrides the signal being demodulated (a collision), the demodulator will abort the tracking process and attempt to acquire the new signal. Failure to find an SFD within the SFD timeout interval will result in a receiver reset and return to acquisition mode.
25
ISL3873B Channel Matched Filter (CMF) Description
The receive section shown in Figure 19 operates on the RAKE receiver principle which maximizes the SNR of the signal by combining the energy of multipath signal components. The RAKE receiver is implemented with a Channel Matched Filter (CMF) using a FIR filter structure with 16 taps. The CMF is programmed by calculating the Channel Impulse Response (CIR) of the channel and mathematically manipulating that to form the tap coefficients of the CMF. Thus, the CMF is set to compensate the channel characteristics that distort the signal. Since the calculation of the CIR is inaccurate at low SNR or in the presence of strong CW interference, the chip has thresholds (CR 36 to 39) that are set to substitute a default CMF shape under those conditions. This default CMF shape is designed to compensate only the known transmit and receive non linearity. necessary frequency information for seeding the NCO operation.
Data Decoder and Descrambler Description
The data decoder that implements the desired DQPSK coding/decoding as shown in Table 11. The data is formed into pairs of bits called dibits. The left bit of the pair is the first in time. This coding scheme results from differential coding of the dibits. Vector rotation is counterclockwise for a positive phase shift, but can be reversed with bit 7 or 6 of CR 1. For DBPSK, the decoding is simple differential decoding.
TABLE 11. DQPSK DATA DECODER PHASE SHIFT 0 +90 +180 -90 DIBIT PATTERN (D0, D1) D0 IS FIRST IN TIME 00 01 11 10
PN Correlators Description
There are two types of correlators in the ISL3873B baseband processor. The first is a parallel matched filter correlator that correlates for the Barker sequence used in preamble, header, and PSK data modes. This Barker code correlator is designed to handle BPSK spreading with carrier offsets up to 50ppm and 11 chips per symbol. Since the spreading is BPSK, the correlator is implemented with two real correlators, one for the I and one for the Q Channel. The same Barker sequence is always used for both I and Q correlators. These correlators are time invariant matched filters otherwise known as parallel correlators. They use one sample per chip for correlation although two samples per chip are processed. The correlator despreads the samples from the chip rate back to the original symbol rate giving 10.4dB processing gain for 11 chips per symbol. While despreading the desired signal, the correlator spreads the energy of any non correlating interfering signal. The second form of correlator is the parallel correlator bank used for detection of the CCK modulation. For the CCK modes, the 64 wide bank of parallel correlators is implemented with a Fast CCK Transform to correlate 8 or 128 code possibilities. This greatly simplifies the circuitry of the correlation function. It is followed by a biggest picker which finds the biggest of 8 or 128 correlator outputs depending on the rate. This is translated into 3 or 7 data bits. The detected output phase determines the last bit of the symbol.
The data scrambler and de-scrambler are self synchronizing circuits. They consist of a 7-bit shift register with feedback of some of the taps of the register. The scrambler is designed to ensure smearing of the discrete spectrum lines produced by the PN code. One thing to keep in mind is that both the differential decoding and the descrambling cause error extension or burst errors. This is due to two properties of the processing. First, the differential decoding process causes errors to occur on pairs of symbols. When a symbol's phase is in error, the next symbol will also be decoded wrong since the data is encoded in the change in phase from one symbol to the next. Thus, two errors are made on two successive symbols. Therefore up to 4 bits may be wrong although on the average only 2 are. In QPSK mode, these may occur next to one another or separated by up to 2 bits. In the CCK mode, when a symbol decision error is made, up to 6 bits may be in error although on average only 3 bits will be in error. Secondly, when the bits are processed by the descrambler, these errors are further extended. The descrambler is a 7-bit shift register with two taps exclusive or'ed with the bit stream. Thus, each error is extended by a factor of three. Multiple errors can be spaced the same as the tap spacing, so they can be canceled in the descrambler. In this case, two wrongs do make a right. Given all that, if a single error is made the whole packet is discarded anyway, so the error extension property has no effect on the packet error rate. It should be taken into account if a forward error correction scheme is contemplated. Descrambling is self synchronizing and is done by a polynomial division using a prescribed polynomial. A shift register holds the last quotient and the output is the exclusiveor of the data and the sum of taps in the shift register.
Data Demodulation and Tracking Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks tracked by the symbol timing loop (bit sync) as shown in Figure 18. The frequency and phase of the signal is corrected using the NCO that is driven by the phase locked loop. Averaging the phase errors over 10 symbols gives the
26
ISL3873B
SAMPLES AT 2X CHIP RATE
CORRELATION PEAK
CORRELATION TIME EARLY ON-TIME LATE
T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING E PSEUDO NOISE(PN) SEQUENCE WITH THE RECEIVED SIGNAL
T0 + 1 SYMBOL CORRELATOR OUTPUT REPEATS
T0 + 2 SYMBOLS
FIGURE 18. CORRELATION PROCESS
Data Demodulation in the CCK Modes
In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two highest data rates. It is slaved to the low rate processor which it depends on for acquisition of initial timing and phase tracking information. The low rate section acquires the signal, locks up symbol and carrier tracking loops, and determines the data rate to be used for the MPDU data. The demodulator for the CCK modes takes over when the preamble and header have been acquired and processed. On the last bit of the header, the phase of the signal is captured and used as a phase reference for the high rate differential demodulator. The signal from the A/D converters is carrier frequency and phase corrected by a DESPIN stage. This removes the frequency offset and aligns the I and Q Channels properly for the correlators. The sample rate is decimated to 11MSPS for the correlators after the DESPIN since the data is now synchronous in time. There are 64 I and 64 Q channel correlator outputs. The demodulator knows the symbol timing, so the correlation is batch processed over each symbol. The correlation outputs from the correlator are compared to each other in a biggest picker and the chosen one determines 7 bits of the symbol. The phase of the chosen one determines one more bit for a total of 8 bits per symbol. Seven bits come from which of the 128 correlators had the largest output and the last is determined from the differential demod of the phase. In the 5.5Mbps mode, only 8 of the correlator outputs are monitored. This demodulates 3 bits for which of 8 correlators had the largest output and one more for the phase demodulation of that output for a total of 4 bits per symbol.
first part of the acquisition after the AGC has settled and the antenna selected. The same data is used for CMF calculations and equalizer training. Once the equalizer has been set up, it is used to process the incoming symbols in a decision feedback manner. After the Fast Walsh transform is performed, the detected symbols are corrected for ICI before the bigger picker where the symbol decision process is performed. Once a symbol has been demodulated, the calculated residual energy from that symbol is subtracted from the incoming data for the next symbol. That corrects for the ISI component. The DFE is not adapted during the packet as the channel impulse response is not expected to vary significantly during that brief time. Register CR10 bits 4 and 5 can disable these equalizers separately.
Tracking
Carrier tracking is performed on the de-rotated signal samples from the complex multiplier in a four phase Costas loop. This forms the error term that is integrated in the lead/lag filter for the NCO, closing the loop. Tracking is only measured when there is a chip transition. Note that this tracking is dependent on a positive SNR in the chip rate bandwidth. The symbol clock is tracked by a sample interpolator that can adjust the sample timing forwards and backwards by 72 increments of 1/8th chip. This approach means that the ISL3873B can only track an offset in timing for a finite interval before the limits of the interpolator are reached. Thus, continuous demodulation is not possible.
Locked Oscillator Tracking
Symbol tracking can be slaved to the carrier offset tracking for improved performance as long as at both the transmitting and the receiving radios, the bit clocks and carrier frequency clocks are locked to common crystal oscillators. A bit carried in the SERVICE field (bit 2) indicates whether or not the transmitter has locked clocks. When the same bit is set at the receiver (CR6 bit 2), the receiver knows it can track the bit clock by counting down the carrier tracking offset. This is much more accurate than tracking the bit clock directly. CR33 bit 6 can enable or disable this capability.
Equalizer Description
The ISL3873B employs a Decision Feedback Equalizer (DFE) to improve performance in the presence of significant multipath distortion. The DFE combats Inter Chip Interference (ICI) and Inter Symbol Interference (ISI). The equalizer is trained on the sample data collected during the 27
ISL3873B
VDDA (ANALOG)
GND (ANALOG)
VDD (DIGITAL)
GND (DIGITAL)
RX_IF_DET RX_IF_AGC RX_RF_AGC 6-BIT DAC DIVERSITY CONTROL AGC CONTROL CLEAR CHANNEL ASSESSMENT/ SIGNAL QUALITY CMF TRAINING
CCA to MAC (INTERNAL)
ANT SEL
CORRELATOR BARKER
8 PEAK EXTRACT. 8
BIT SYNC
CHANNEL MATCHED FILTER
DOWN CONVERT
RXI
6-BIT A/D
INTERPOLATING BUFFER
6
DPSK DEMOD
INTERNAL TRANSMIT AND RECEIVE SIGNALS TO MAC RXD TO MAC
RXQ
6-BIT A/D
6
RX_DATA DESCRAMBLER
RXCLK TO MAC
PREAMBLE/HEADER CRC-16 DETECT
SYMBOL TRACKING
MD_RDY TO MAC
NCO
EQUAL. BIAS ADDER
CCK CORREL
SYMBOL DECISION
COHERENT TIMING INTEGRATOR
DECISION FEEDBACK EQUALIZER LOOP FILTER
ANTSEL ANTSEL
TEST CONTROL
MUX
ANTENNA SWITCH CONTROL
RECEIVE STATE MACHINE
6-BIT DAC
TXI
MUX
6-BIT DAC
TXQ
TIMING GENERATOR MCLK
RESET
RX_PE
MCLK
FIGURE 19. DSSS BASEBAND PROCESSOR, RECEIVE SECTION
28
ISL3873B Demodulator Performance
This section indicates the typical performance measures for a radio design. The performance data below should be used as a guide. In general, the actual performance depends on the application, interference environment, RF/IF implementation and radio component selection. the link do not have locked oscillators, then symbol tracking is done by a conventional early-late chip tracking method.
Eb/N0 7 8 9 10 11 12 1.E+00 1.E-01 1.E-02 BER 2.0 1.E-03 BER 1.0 THY 1, 2 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 BER
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and energy efficient in packet mode communications. The demodulator uses coherent processing for data demodulation. The figures below show the performance of the baseband processor when used in conjunction with the HFA3783 IF and the PRISM recommended IF filters. Off the shelf test equipment are used for the RF processing. The curves should be used as a guide to assess performance in a complete implementation. Factors for carrier phase noise, multipath, and other degradations will need to be considered on an implementation by implementation basis in order to predict the overall performance of each individual system. Figure 18 shows the curves for theoretical DBPSK/DQPSK demodulation with coherent demodulation and descrambling as well as the PRISM performance measured for DBPSK and DQPSK. The theoretical performance for DBPSK and DQPSK are the same as shown on the diagram. Figure 21 shows the theoretical and actual performance of the CCK modes. The losses in both figures include RF and IF radio losses; they do not reflect the ISL3873B losses alone. The ISL3873B baseband processing losses from theoretical are, by themselves, a small percentage of the overall loss. The PRISM demodulator performs with an implementation loss of less than 4dB from theoretical in a AWGN environment with low phase noise local oscillators. For the 1 and 2Mbps modes, the observed errors occurred in groups of 4 and 6 errors. This is because of the error extension properties of differential decoding and descrambling. For the 5.5 and 11Mbps modes, the errors occur in symbols of 4 or 8 bits each and are further extended by the descrambling. Therefore the error patterns are less well defined.
FIGURE 20. BER vs. Eb/N0 PERFORMANCE FOR PSK MODES
Eb/N0 9 10
1.E+00 1.E-01 1.E-02 1.E-03 BER 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09
5
6
7
8
11
12
13
14
BER 11
THY 11 THY 5.5 BER 5.5
FIGURE 21. BER vs. Eb/N0 PERFORMANCE FOR CCK MODES
Carrier Offset Frequency Performance
The correlators used for acquisition for all modes and for demodulation in the 1 and 2Mbps modes are time invariant matched filter correlators otherwise known as parallel correlators. They use two samples per chip and are tapped at every other shift register stage. Their performance with carrier frequency offsets is determined by the phase roll rate due to the offset. For an offset of +50ppm (combined for both TX and RX) will cause the carrier to phase roll 22.5 degrees over the length of the correlator. This causes a loss of 0.22dB in correlation magnitude which translates directly to Eb/N0 performance loss. In the PRISM chip design, the carrier phase locked loop is inactive during acquisition. During tracking, the carrier tracking loop corrects for offset, so that no degradation is noted. In the presence of high multipath and high SNR, however, some degradation is expected.
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data clock offsets of up to 25ppm for each end of the link (TX and RX). This effects both the acquisition and the tracking performance of the demodulator. The budget for clock offset error is 0.75dB at 50ppm. No appreciable degradation was seen for operation in AWGN at 50ppm. Symbol tracking is accomplished by one of two methods. If both ends of the link employ locked oscillators for their bit timing and carrier frequency generation, symbol tracking is done by dividing down the carrier frequency offset. If either one of the ends of
29
ISL3873B RSSI Performance
The RSSI value is reported on CR62 in hex and is linear with signal level in dB. Figure 22 shows the RSSI curve measured on a whole evaluation radio. This takes into account the full gain adjust range of all radio parts. To get signal level in dBm on a radio, simply subtract the RSSI value in decimal from 100.
100 90 80 70 60 50 40 120 RSSI 100 80 RSSI IN DE 30 20 10 0 -10 -5 0 5 10 15 20 25 PER MEAN STDDEV
SNR IN THE SPREAD BANDWIDTH AT 1Mbps 60 40
FIGURE 23. SIGNAL QUALITY MEASURE AND PER vs SNR
ED Threshold
20 0 -100
-80
-60
-40
-20
0
SIGNAL LEVEL IN dBm
The performance of the ED threshold is shown in Figure 24. Setting this threshold will effect CCA only. Using ED as part of the CCA measure will allow deferral to large signals even if they are not correlated to the desired spread signals. ED can be read from CR61 bit 4. Using ED and RSSI can assist the MAC in determining the presence of non correlating signals such as frequency hoppers or microwave ovens. For example, the MAC can elect to try to transmit over microwave oven interference but not count the results in rate shifting algorithms.
40 ED THRESHOLD VALUE IN DECIMAL
FIGURE 22. RSSI vs SIGNAL LEVEL
Signal Quality Estimate
A signal quality measure is available on CR51 for use by the MAC. This measure is the SNR in the carrier tracking loop and can be used to determine when the demodulator is working near to the noise floor and likely to make errors. Figure 23 shows the performance of the SQ measure versus signal to noise level.
30
20
10
0
STARTS MISSING MISSING
-10
0
10
20 SNR IN SPREAD BANDWIDTH
30
40
FIGURE 24. ED THRESHOLD vs SNR IN dB AT 1Mbps
30
ISL3873B Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Bit 3:0 Part Code 3 = HFA3863 series Version Code 0 = 3863 Version CONFIGURATION REGISTER 1 ADDRESS (02h) R/W I/O POLARITY This register is used to define the phase of clocks and other interface signals. 00h is normal setting. Bit 7 This control bit selects the phase of the receive carrier rotation sense. Logic 1 = Inverted rotation (CW), Invert Q in. Logic 0 = normal rotation (CCW). This control bit selects the phase of the transmit carrier rotation sense. Logic 1 = Inverted rotation (CW), Invert Q out. Logic 0 = normal rotation (CCW). This control bit selects the phase of the transmit output clock (TXCLK) pin. Logic 1 = Inverted TXCLK. Logic 0 = NON-Inverted TXCLK. This control bit selects the active level of the Transmit Ready (TX_RDY) output which is an output pin at the test port, pin. Logic 1 = TX_RDY Active 0. Logic 0 = TX_RDY Active 1. This control bit selects the active level of the transmit enable (TX_PE) input pin. Logic 1 = TX_PE Active 0. Logic 0 = TX_PE Active 1. This control bit selects the active level of the Clear Channel Assessment (CCA) output pin. Logic 1 = CCA Active 1. Logic 0 = CCA Active 0. This control bit selects the active level of the MD_RDY output pin. Logic 1 = MD_RDY is Active 0. Logic 0 = MD_RDY is Active 1. This controls the phase of the RX_CLK output. Logic 1 = Invert Clk. Logic 0 = Non-Inverted Clk.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIGURATION REGISTER 2 ADDRESS (04h) R/W RX CONFIGURE Write to control, Read to verify control, setup while TX_PE and RX_PE are low Bits 7:1 Bit 0 Reserved. Initialization. 0 = Normal Operation. 1 = Soft Initialization of learned behavior registers such as DCoffset, NoiseFloor, FAR, RecPacketsNOcs1, and RecPacketsUSEdef. Holds AGC logic reset. At part initialization, must be set, then after CR47 is loaded, cleared.
CONFIGURATION REGISTER 3 ADDRESS (06h) R/W TX PREAMBLE LENGTH FOR SHORT PREAMBLE Bits 0 - 7 This register contains the count for the Preamble length counter for short preambles selected by CR5 bit 3. Setup while TX_PE is low. For IEEE 802.11 use38h. For other than IEEE 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value is 56d = 38h. A 2 symbol TX power amplifier ramp up is added to programmed value.
31
ISL3873B
CONFIGURATION REGISTER 4 ADDRESS (08h) R/W TX PREAMBLE LENGTH FOR LONG PREAMBLE Bits 0 - 7 This register contains the count for the Preamble length counter for long preambles selected with CR5 bit 3 or CR11 bit 4. Setup while TX_PE is low. For IEEE 802.11 use 80h. For other than IEEE 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value is 56d = 38h. A 2 symbol TX power amplifier ramp up is added to programmed value. If you program 128 you get 130. CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD Bits 7:5 Bit 4 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. TX/RX filter / CMF weight select. 0 = US. 1 = Japan for channel 14 compliance. Select preamble mode. 0 = Normal, long preamble interoperable with 1 and 2Mbps legacy equipment. 1 = short preamble and header mode (optional in 802.11). Reserved, must be set to 0. TX data Rate. Must be set at least 2s before needed in TX frame. This selects TX signal field code from the registers above. 00 = DBPSK - 11 chip sequence (1Mbps). 01 = DQPSK - 11 chip sequence (2Mbps). 10 = CCK - 8 chip sequence (5.5Mbps). 11 = CCK - 8 chip sequence (11Mbps). CONFIGURATION REGISTER 6 ADDRESS (0Ch) R/W TX SERVICE FIELD Bits 7:0 Bit 7 may be employed by the MAC in 802.11 situations to resolve an ambiguity in the length field when in the 11Mbps mode. Bit 2 should be set to a 1 where the reference oscillator of the radio is common for both the carrier frequency and the data clock. All other bits should be set to 0 to ensure compatibility. CONFIGURATION REGISTER 7 ADDRESS (0Eh) R/W TX LENGTH FIELD (HIGH) Bits 7:0 This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte combined with the lower byte indicates the number of microseconds the data packet will take. CONFIGURATION REGISTER 8 ADDRESS (10h) R/W TX LENGTH FIELD (LOW) Bits 7:0 This 8-bit register contains the lower byte (bits 0-7) of the transmit Length Field described in the Header. This byte combined with the higher byte indicates the number of microseconds the data packet will take. CONFIGURATION REGISTER 9 ADDRESS (12h) R/W TX CONFIGURE Bit 7 CCA sample mode time. 0 = 18.7s. 1 = 15.8s. CCA mode. 00 - CCA is based only on ED. 01 - CCA is based on (CS1 OR SQ1). 10 - CCA is based on (ED AND (CS1 OR SQ1)). 11 - CCA is based on (ED OR (CS1 OR SQ1)). TX test modes (set CR5 bits 1:0 to 00 also), (set CR32 = 0CH). 0 = Alternating bits for carrier suppression test. 1 = all chips set to 1 for CW carrier. This allows frequency measurement. Enable TX test modes. 0 = normal operation. 1 = Invoke tests described by bit 4. Antenna choice for TX when TX antenna diversity is disabled. 0 = Set AntSel low. 1 = Set AntSel high.
Bits 3
Bit 2 Bits 1:0
Bits 6:5
Bit 4
Bit 3
Bit 2
32
ISL3873B
CONFIGURATION REGISTER 9 ADDRESS (12h) R/W TX CONFIGURE Bit 1 TX Antenna Mode. 0 = Disable diversity, set AntSel pin to value in bit 2. 1 = Enable diversity, set AntSel pin to antenna for which last valid received header CRC occurred. Must be set to 0. CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE Bit 7 AGC freeze during packet. 0 = Disable (do not disable unless MAC can handle baseband processor aborting during MPDU reception). 1 = Enable. CIR estimate/ Dot product clock control. 0 = on during acquisition. 1 = only on after detect. ISI equalizer control. 0 = enable equalizer. 1 = disable equalizer. ICI equalizer control. 0 = enable equalizer. 1 = disable equalizer. MD_RDY control. 0 = After CRC16. 1 = After SFD. Slot diversity mode control. 0 = disabled, Antenna diversity on for entire slot. 1 = enabled, Antenna diversity disabled for last half of slot - saves acquisition time, use in system where nodes are slot aligned. Antenna choice for Receiver when single antenna acquisition is selected. 0 = Antenna select pin low. 1 = Antenna select pin high. Single or dual antenna acquire. 0 = dual antenna for diversity acquisition. 1 = single antenna. CONFIGURATION REGISTER 11 ADDRESS (16h) R/W RX-TX CONFIGURE Bit 7 Continuous internal RX 22 and 44MHz clocks; (Only Reset active will stop). 0 = normal. 1 = continuous, overrides CR10 bit 6. A/D input coupling. 0 = DC. 1 = AC (external bias network required). Reserved. Short Preamble test mode. 0 = use CR3 for short preamble. 1 = run TX and RX short preamble using preamble length in CR4. CCA mode. 0 = normal (raw) mode CCA. CCA will immediately respond to changes in ED, CS1, and SQ1 as configured. 1 = Sampled mode CCA. CCA will update once per slot (20s), will be valid at 18.7s or 15.8s as determined by CR9 bit 7. Precursor value in CIR estimate. CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 Bit 7 All DAC and A/D clock source control. 0 = normal internal clocks. 1 = clock via SDI pin.
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 6
Bit 5 Bit 4
Bit 3
Bits 2:0
33
ISL3873B
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued) Bit 6 TX DAC clock. 0 = enable. 1 = disable. RX DAC clock. 0 = enable. 1 = disable. I DAC clock. 0 = enable. 1 = disable. Q DAC clock. 0 = enable. 1 = disable. RF A/D clock. 0 = enable. 1 = disable. I A/D clock. 0 = enable. 1 = disable. Q A/D clock. 0 = enable. 1 = disable. CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2 Bit 7 Standby. 1 = enable. 0 = disable. SLEEPTX. 1 = enable. 0 = disable. SLEEP RX. 1 = enable. 0 = disable. SLEEP IQ. 1 = enable. 0 = disable. Analog TX Shut_down. 1 = enable. 0 = disable. Analog RX Shut_down. 1 = enable. 0 = disable. Analog Standby. 1 = enable. 0 = disable. Enable manual control of mixed signal power down signals using bits 1:7. 1 = enable. 0 = disable, normal operation (devices controlled by RESET, TX_PE, RX_PE). CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3 Bit 7 Digital format, select output of I/Q and RF A/D converters. 0 = 2's complement (normal). 1 = binary.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
34
ISL3873B
CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3 (Continued) Bits 6:4 I/Q DAC input control. This DAC gives an analog look at various internal digital signals that are suitable for analog representation. 000 = normal (TX filter). 001 = down converter output. 010 = E/L integrator - upper 6 bits of the TCHIPacc on (Q) and zeros on (I). 011 = I/ Q A/D's. 100 = Bigger picker output. Upper 6 bits of FWT_I winner and FWT_Q winner. 101 = CMF weights - upper 6 bits of all 16 CMF weights are circularly shifted with full scale negative sync pulse interleaved between them. 110 = Test Bus pins (5:0) when configured as inputs, CR32(4), ((5:0) to both I and Q inputs). 111 = Barker Correlator/ low rate samples - as selected by bit 7 CR32. Enable test bus into RX and TX DAC (if below bit 2 is 0). 0 = normal. 1 = enable. Enable RF A/D into RX DAC. 0 = normal. 1 = enable. VRbit1. VRbit0. CONFIGURATION REGISTER 15 ADDRESS (1Eh) R/W AGC GAIN CLIP Bit 7 Bits 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC gain clip (7-bit value, 0-127) this is the attenuator accumulator upper limit. The lower limit is 0. CONFIGURATION REGISTER 16 ADDRESS (20h) R/W AGC SATURATION COUNTS Bits 7:4 Bits 3:0 AGC mid Saturation counts (0-15 range) these are the counts to kick in the low and mid attenuator steps (CR28). AGC low Saturation Count (0-15 range). CONFIGURATION REGISTER 17 ADDRESS (22h) R/W AGC RF PAD VALUE Bit 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. RXRF_AGC pad value to use in the RSSI calculation, Range 0 - 63dB (nominally 30dB). CONFIGURATION REGISTER 18 ADDRESS (24h) R/W AGC HI SAT Bits 7:4 AGC high saturation attenuation value (0-30). Note: hi saturation attenuation step actual value is programmed value times 2. This attenuation step will occur if the # of I and Q sats is greater than hi saturation count. AGC hi sat count (0-15 range). CONFIGURATION REGISTER 19 ADDRESS (26h) R/W AGC LOCK IN LEVEL Bits 7:5 CW detector scale multiplication factor. (xxxx.x). See CR35 and CR 49. Set to 00h for forcing CW detect always active. Set to 0Fh for forcing CW detector always inactive. AGC Lock-in level (0-7.5 range). Note this is the inner lock window. CONFIGURATION REGISTER 20 ADDRESS (28h) R/W AGC LOCK WINDOW POS. Bits 7:5 Bit 4:0 AGC max lock count for antenna search. The number of updates required to lock AGC must be less than or equal to this count for antenna diversity search to be allowed to run. Range 0 to 7. AGC Lock Window positive side (0-15.5 range). Note: this is the outer lock window. CONFIGURATION REGISTER 21 ADDRESS (2Ah) R/W AGC BACKOFF Bits 7,6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 3
Bit 2
Bit 1 Bit 0
Bits 3:0
Bits 4:0
35
ISL3873B
CONFIGURATION REGISTER 21 ADDRESS (2Ah) R/W AGC BACKOFF Bits 5:0 AGC Backoff (xxxxx.x, 0-31.5 range) in half dB steps. This sets the operating headroom in the I and Q ADCs. CONFIGURATION REGISTER 22 ADDRESS (2Ch) R/W AGC LOOKUP TABLE ADDRESS Bits 7,6 Bits 5 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC Look up table read control bit. 1 = Read AGC table at address given below. 0 = Read contents of CR23. AGC lookup table address (32 address bits). CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC TABLE DATA Bits 7 Bits 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC look up table data, unsigned. CONFIGURATION REGISTER 24 ADDRESS (30h) R/W AGC LOOP GAIN Bits 7 Bit 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC loop gain (0.xxxx - x.00000, 0 - 1.0000 range), nominally 0.7. CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC RX_IF AND RF Bits 7 AGC RX_RF, This input drives the RX-RF control if AGC override Enable is set to 1. When Polarity bit (CR26[6]) is zero: 1 = removes 30dB pad. 0 = inserts 30dB pad. AGC RX_IF, This CR is input to RF-IF DAC if AGC override Enable (CR 26[2]) is set to 1. CONFIGURATION REGISTER 26 ADDRESS (34h) R/W AGC TEST MODES Bits 7 AGC continuous update. 0 = disable, no updates during AGC freeze. 1 = allow updates during freeze AGC and AGC_lock. See also CR17[7]. rxRFAGC polarity control. 0 = normal. 1 = invert. AGC extra update disable. Allows final 32 sample update tweak after AGC_lock is declared. 0 = enable an extra update. 1 = disable extra update. R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. AGC override Enable. 0 = normal, disabled. 1 = enabled, CR25 controls receiver gain in both RF and IF via RXRF_AGC and RXIF_AGC lines. AGC 2nd antenna power abort. 0 = AGC lock on 2nd antenna is required to finish antenna dwell. 1 = abort 2nd antenna lock search immediately if power is lower on 2nd antenna than on 1st antenna. AGC Sat Step disable if within CR29[7:5] window. 0 = disable sat step. 1 = enable sat step. CONFIGURATION REGISTER ADDRESS 27 (36h) R/W AGC RF THRESHOLD Bit 7 RXRF AGC disable. 0 = normal. 1 = disables threshold. RF AGC threshold (0-64 range). The RxRf_Agc pad is removed if the AGC voltage falls below this threshold.
Bits 4:0
Bits 6:0
Bit 6
Bit 5
Bits 3:4 Bit 2
Bit 1
Bit 0
Bits 6:0
36
ISL3873B
CONFIGURATION REGISTER ADDRESS 28 (38h) R/W AGC LOW SAT ATTENUATOR Bits 7:4 Mid saturation attenuation (0-30 range). Note: mid saturation attenuation is programmed as this value times 2. The mid and low attenuator steps will occur if the number of I and Q saturations are greater than the mid and low saturation counts set by CR16. low saturation attenuation (0-15 range). CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC LOCK WINDOW NEGATIVE SIDE Bits 7:5 Bits 4:0 AGC Saturation Block Level, 1xx.x, range 4.0 to 7.5 dB. Disable saturation attenuation step if less than or equal to this level. AGC lock window negative side. (0-15.5 range) (this is the outer lock window) Note: set as a positive number, logic will convert to negative. CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR Bits 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Carrier Sense 2 (CS2) scale factor (0-7.875 range) (000000 - 111111). CONFIGURATION REGISTER 31 ADDRESS (3Eh) TX POWER CONTROL Bits 7:1 Bit 0 Sets the transmit power. 7 bits to DAC input, -64 to 63 range. Note: rising edge of TXPE is required for value in CR 31 to be applied to DAC. R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1 Bit 7 Selection bit for DAC input test mode 7. 0 = Barker. 1 = Low rate I/Q samples. force high rate mode. 0 = normal. 1 = force high rate mode. Length Field counter. 0 = disable (802.11 systems, length field is in microseconds, not bits). 1 = enabled - counts bits, resets RX. Tristate test bus and enable inputs. 0 = Normal. 1 = enable inputs on test bus. Disable spread sequence for 1 and 2Mbps. 0 = Normal. 1 = disabled. Disable scrambler. 0 = normal scrambler operation. 1 = scrambler disabled (taps set to 0). PN generator enable (RX 44MHz clock). For factory test only. 0 = not enabled. 1 = enabled. Bit must first be written to a `0' before a `1' to initialize logic. PN generator enable (RX 22MHz clock). For factory test only. 0 = not enabled. 1 = enabled. Bit must first be written to a `0' before a `1' to initialize logic. CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2 Bit 7 Coherent AGC disable. 0 = normal, enabled. 1 = disable.
Bits 3:0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
37
ISL3873B
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2 (Continued) Bit 6 Time Tracking Mode. 0 = enable detection of the Service field bit showing that the carrier and bit timing are locked to the same oscillator. 1 = disable detection and force locked time tracking. Note. for automatic locked time tracking operation, bit 2 of the received Service field as well as bit 2 of CR6 of the receiver must be a "1". DC offset compensation control. Final digital DC input offset compensation. 0 = enable DC offset compensation. 1 = disable DC offset compensation. Bypass I/Q A/Ds. 0 = disable bypass. 1 = 4 MSBs of I/Q data are input on test bus. TESTin 3:0 is [5:2], TESTin 7:4 is Q[5:2], LSBs are zeroed. disable time adjust during packet. Note: this turns off bit tracking. 0 = normal. 1 = time tracking disabled (overrides bit 6 also). Internal digital loop back mode (SDI pin becomes LOCK input to acquisition block). 0 = normal chip operation loop back disabled. 1 = loop back enabled, A/D and D/A converters bypassed, chip will not respond to external signals. enable PN to lower test bus address (2-0). For factory test. 0 = normal. 1 = PN to test bus address. enable PN to upper test bus address (7-3). For factory test. 0 = normal. 1 = PN to test bus address. CONFIGURATION REGISTER ADDRESS 34 (44h) R/W TEST BUS ADDRESS Bits 7:0 Address bits for various tests. See Tech Brief #TB394 for a description of the test modes. CONFIGURATION REGISTER ADDRESS 35 (46h) R/W ED THRESHOLD Bit 7 Energy Detect Threshold control. 0 = threshold is relative to noise floor. 1 = threshold is absolute. ED Threshold. Range 0 - 127dBm. RSSI > threshold triggers ED. CONFIGURATION REGISTER ADDRESS 36 (48h) R/W DELAY SPREAD THRESHOLD FOR CMF CONTROL Bit 7:5 Bits 4:0 Delay spread count. Range 0 - 7. Used for evaluation only. Delay spread threshold. 0.xxxx. This and the next 3 thresholds are used in the following formula to determine which CMF weights to use. CW detect is not configurable. If (CW and RSSI < (CW RSSI threshold + NoiseFloor)) or (no CW and RSSI < (SNR threshold #1 + NoiseFloor)) or (no CW and delay spread < threshold and RSSI < (SNR threshold #2 + NoiseFloor)) then; use Default CMF weights, else, use Calculated CMF weights. CONFIGURATION REGISTER ADDRESS 37 (4Ah) R/W CW RSSI THRESHOLD FOR CMF CONTROL Bit 7 Bit 6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Force default CMF weights. 0 = normal. 1 = force default CMF weights. Force calculated CMF weights. 0 = normal. 1 = force calculated CMF weights. Note: this cannot be combined with bit 6. A "1" on both will produce undefined results. CW RSSI threshold, range 0 to 31dB.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 6:0
Bit 5
Bits 4:0
38
ISL3873B
CONFIGURATION REGISTER ADDRESS 38 (4Ch) R/W SNR THRESHOLD #1 FOR CMF CONTROL Bits 7:4 Bits 3:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. SNR threshold #1 range 0 to 15dB. CONFIGURATION REGISTER ADDRESS 39 (4Eh) R/W SNR THRESHOLD #2 FOR CMF CONTROL Bits 7:4 Bits 4:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. SNR threshold #2, range 0 to 31dB. CONFIGURATION REGISTER ADDRESS 40 (50h) R/W DC OFFSET THRESHOLD Bits 7:6 Bits 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. DC offset Threshold, range 0 to 63dB. RSSI > (threshold + NoiseFloor) enables DC offset calculation and compensation. CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE/HEADER LEAD COEFFICIENT Bit 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Preamble Lead Coefficient (0-4 range) (000000 - 100000). CONFIGURATION REGISTER ADDRESS 42 (54h) R/W PREAMBLE/HEADER LAG COEFFICIENT Bit 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Preamble Lag Coefficient (0-4 range) (000000 - 100000). CONFIGURATION REGISTER ADDRESS 43 (56h) R/W MPDU LEAD COEFFICIENT Bit 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Header Lead Coefficient (0-4 range) (000000 - 100000). CONFIGURATION REGISTER ADDRESS 44 (58h) R/W MPDU LAG COEFFICIENT Bit 7:6 Bit 5:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Header Lag Coefficient (0-4 range) (000000 - 100000). CONFIGURATION REGISTER ADDRESS 45 (5Ah) R/W FALSE ALARM RATE OF SQ1 Bits 7:0 False alarm rate of SQ1. Enable/disable with CR47 bit 7. Rate = N*32/2^16. For example 01h = 0.05% False Alarm Rate (FAR) and 10h = 0.78% FAR. CONFIGURATION REGISTER ADDRESS 46 (5Ch) R/W ACQUISITION TIMELINE Bit 7 Long Preamble timeline disable. 0 = enable long preamble timeline processing. 1 = disable long preamble timeline processing (process all preambles as if short). Long Preamble timeline diversity metric selection. 0 = H factors. 1 = RSSI. SQ1 threshold #2, range 0 to 7.875. (000.00 - 111.111). Used for verify cycle. CONFIGURATION REGISTER ADDRESS 47 (5Eh) R/W ACQUISITION THRESHOLDS Bit 7 Disable False alarm Rate Processing. 0 = Enable, SQ1 #1 threshold is adjusted in real time by FAR logic. 1 = Disable, SQ1 #1 threshold is set to value of CR 47 (5:0). ED and SQ1 control for acquisition. 0 = SQ1. 1 = ED and SQ1. SQ1 threshold #1, range 0 to 7.875. (000.00 - 111.111). Used for initial detect and initial setting for FAR.
Bit 6
Bits 5:0
Bit 6
Bits 5:0
39
ISL3873B
CONFIGURATION REGISTER ADDRESS 48 (60h) R/W SCRAMBLER SEED, LONG PREAMBLE Bit 7 Bit 6:0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Scrambler seed for long preamble. Bit 3 of CR5 selects CR48 or CR49. CONFIGURATION REGISTER ADDRESS 49 (62h) R/W SCRAMBLER SEED AND READ ONLY REGISTER MUX CONTROL Bit 7 Read only register mux control. 0 = READ ONLY registers read `b' value. 1 = READ ONLY registers read `a' value. Scrambler seed for short preamble. Bit 3 of CR5 selects CR48 or CR49. CONFIGURATION REGISTER ADDRESS 50 (64h) R TEST BUS READ Bit 7:0 a&b: reads value on test bus. CONFIGURATION REGISTER ADDRESS 51 (66h) R SIGNAL QUALITY MEASURE Bit 7:0 a: NOISEfloorAntA [7:0] unsigned, range 0-255. b: measures signal quality based on the SNR in the carrier tracking loop. CONFIGURATION REGISTER ADDRESS 52 (68h) R RECEIVED SIGNAL FIELD Bit 7:0 a: NOISEfloorAntB [7:0] unsigned, range 0-255. b: 8-bit value of received signal field. CONFIGURATION REGISTER ADDRESS 53 (6Ah) R RECEIVED SERVICE FIELD Bit 7:0 a: I DC offset, signed, sxxxx.xx. b: 8-bit value of received service field. CONFIGURATION REGISTER ADDRESS 54 (6Ch) R RECEIVED LENGTH FIELD, LOW Bit 7:0 a: Q DC offset, signed, sxxxx.xx. b: 8-bit value of received length field, low byte. CONFIGURATION REGISTER ADDRESS 55 (6Eh) R RECEIVED LENGTH FIELD, HIGH Bit 7:0 a: Multipath metric, 11111111 (large multipath) to 00000000 (no multipath) on last packet received. b: 8-bit value of received length field, high byte. CONFIGURATION REGISTER ADDRESS 56 (70h) R CALCULATED CRC ON RECEIVED HEADER, LOW Bit 7:0 a: Multipath count. How many of last 15 packets had multipath greater than the programmed threshold (CR36 <7:5>). b: 8-bit value of CRC calculated on header, low byte. CONFIGURATION REGISTER ADDRESS 57 (72h) R CALCULATED CRC ON RECEIVED HEADER, HIGH Bit 7:0 a: Packet signal quality metric. (1, 2, 5.5, 11Mbps) smaller value is poorer quality. Valid for reading after RXPE inactive. b: 8-bit value of CRC calculated on header, high byte. CONFIGURATION REGISTER ADDRESS 58 (74h) R TX POWER MEASUREMENT Bit 7:0 a&b: 8-bit value of transmit power measurement (-128 to 127 range) 64 sample average. CONFIGURATION REGISTER ADDRESS 59 (78h) R RX MEAN POWER Bit 7:0 a: Header Signal Quality Metric. (1, 2Mbps) Smaller value is poorer quality. Valid for reading after RXPE inactive. b: Average power of received signal after log table lookup (0--33 range in dB). Minus 33 is minimum power, 0 is maximum. CONFIGURATION REGISTER ADDRESS 60 (7Ah) R RX_IF_AGC Bit 7 a&b: unused.
Bits 6:0
40
ISL3873B
CONFIGURATION REGISTER ADDRESS 60 (7Ah) R RX_IF_AGC Bits 6:0 a&b: AGC output to the DAC, MSB unused. CONFIGURATION REGISTER ADDRESS 61 (7Ch) R RECEIVE STATUS Bit 7:5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 a&b: unused. a&b: ED, energy detect past threshold. a&b: TX PWR det Register semaphore - a 1 indicates CR58 has updated since last read. a&b: AGC_lock - a 1 indicates AGC is within limits of lock window CR20. a&b: hwStopBHit - a 1 indicates rails hit, AGC updates stopped. a&b: RX_RF_AGC - status of AGC output to RF chip. CONFIGURATION REGISTER ADDRESS 62 (7Eh) R RSSI Bit 7:0 a&b: 8-bit value of Packet RSSI, unsigned, range 0 to 255 dB. CONFIGURATION REGISTER ADDRESS 63 (80h) R RECEIVE STATUS Bit 7:6 a&b: signal field value (HRfieldmatch/QPSKwd_OK). 00 = 1. 01 = 2. 10 = 5.5. 11 = 11. a&b: SFD found. a&b: Short preamble detected. a&b: valid signal field found. a&b: valid CRC 16. a&b: Antenna selected by receiver when last valid header CRC occurred. a&b: not used.
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
41
ISL3873B Plastic Ball Grid Array Packages (BGA)
o
A1 CORNER A1 CORNER I.D.
D
A
V192.14x14
192 BALL PLASTIC BALL GRID ARRAY PACKAGE INCHES SYMBOL A
E
MILLIMETERS MIN 0.31 0.83 0.41 13.90 11.90 MAX 1.40 0.41 0.99 0.51 14.10 12.10 192 0.80 BSC 16 x 16 0.10 0.12 NOTES 7 3 Rev. 1 1/01
MIN 0.012 0.033 0.016 0.547 0.468 192
MAX 0.059 0.016 0.039 0.020 0.555 0.476
A1 A2 b D/E D1/E1
B
TOP VIEW 0.15 MCAB 0.006 0.08 MC 0.003 b
N e
0.032 BSC 16 x 16 0.004 0.005
D1
A1 CORNER A1 CORNER I.D. A B C D E F G H E1 J K L M N P R T e
MD/ME bbb aaa NOTES:
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
S
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. "MD" and "ME" are the maximum ball matrix size for the "D" and "E" dimensions, respectively. 4. "N" is the maximum number of balls for the specific array size. 5. Primary datum C and seating plane are defined by the spherical crowns of the contact balls. 6. Dimension "A" includes standoff height "A1", package body thickness and lid or cap height "A2". 7. Dimension "b" is measured at the maximum ball diameter, parallel to the primary datum C. 8. Pin "A1" is marked on the top and bottom sides adjacent to A1. 9. "S" is measured with respect to datum's A and B and defines the position of the solder balls nearest to package centerlines. When there is an even number of balls in the outer row the value is "S" = e/2.
A
S A BOTTOM VIEW A1 A2 bbb C C A SEATING PLANE SIDE VIEW aaa C ALL ROWS AND COLUMNS
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 42

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